Wafer-scale and universal van der Waals metal semiconductor contact

Two-dimensional semiconductors offer ultrathin body thickness and dangling-bond-free surfaces, enabling aggressive scaling and reduced short-channel effects for future transistors. Yet forming high-quality metal contacts on these atomically thin, delicate lattices remains challenging. Conventional high-energy metallization techniques (thermal/e-beam evaporation, sputtering, CVD) bombard 2D materials with energetic atoms or clusters, causing lattice damage and interfacial reactions that lead to strong Fermi level pinning, uncontrollable Schottky barriers, and large contact resistances. Overcoming contact-induced degradation is crucial to preserve intrinsic properties and realize high-performance devices based on 2D semiconductors.

Low-energy vdW integration has been explored to mitigate contact damage by avoiding chemical bonding at the interface. Direct evaporation of low-melting-point metals or semimetals (e.g., In, Bi, Sn) can form atomically clean vdW gaps and minimize Fermi level pinning, achieving contact resistances down to ~0.12 kΩ·µm. However, such approaches are limited to specific metals and can raise concerns about thermal stability. Alternatively, transferred metal electrodes laminated onto 2D materials avoid high-energy deposition at the interface and approach Schottky–Mott behavior, but mechanical peeling/transfer works only for a few low-adhesion metals (Ag, Au, Pt, Pd) and is incompatible with most industry-relevant high-adhesion metals (Al, W, Ni, Co, Mo, Ti, Ta). A selenium buffer layer deposited directly on the 2D surface followed by metal evaporation and thermal removal can yield vdW contacts with more metals, but still exposes the 2D lattice to high-energy Se deposition and lacks demonstrated scalability. Thus, a damage-free, scalable, and universal vdW integration method for diverse metals/semiconductors has remained elusive.

The authors propose a wafer-scale vdW contact formation using a thermally decomposable polymer buffer, poly(propylene carbonate) (PPC). Devices are fabricated on Si/SiO2 substrates (300 nm SiO2) with CVD-grown WSe2 (monolayer/bilayer). Process: (1) Spin-coat 10 wt% PPC in anisole at 5000 rpm; prebake at 120 °C for 2 min to form ~450 nm PPC film. (2) Deposit 60 nm metal (e.g., Au, Ag, Al, Ti, Cr, Ni, Cu, Co, Pd) by standard thermal evaporation under ~5×10⁻⁴ Pa using a stencil mask. The PPC thickness protects the 2D semiconductor from energetic species and chemical bonding during deposition. (3) Anneal at 250 °C for 30 min in N2 (glove box) to dry-decompose PPC into gases, which leave the stack, allowing the metal to settle onto the semiconductor via vdW interaction, forming an atomically clean, sharp interface. XPS verifies residue-free decomposition. The process is compatible with wafer-scale integration; a 4-inch wafer with ~25,000 vdW contacts was demonstrated. Interface characterization: Cross-sectional SEM and high-resolution TEM reveal a clean metal–semiconductor interface with a vdW gap ~0.3 nm. AFM characterization is enabled by peeling off the metal electrode encapsulated in a PPC overlayer; the peeled metal’s bottom surface is flipped for AFM, and the exposed 2D surface is also scanned, evidencing cleanliness and flatness. Optical (Raman/PL) measurements confirm negligible strain/doping introduced by the process. Electrical testing: Back-gated WSe2 transistors (bilayer ~1.4 nm) with L = 50 µm and W = 90–135 µm are measured in vacuum at room temperature using a Keysight B2900A. Identical device geometries with conventional evaporated contacts serve as controls. Extension to other materials: vdW contacts are also implemented on other 2D semiconductors (MoS2, WS2, GeAs, MoTe2) and 3D semiconductors (IGZO, Ge, GaAs, perovskite CsPbX3). Additional material syntheses: WSe2/WS2/MoS2 by CVD (e.g., WSe2 at 1170 °C; WS2 at 1200 °C; MoS2 at 650 °C), MoTe2 by tellurization of ~3 nm Mo at 550 °C (final ~7 nm MoTe2), IGZO by RF sputtering (10 nm, 50 W, 0.7 Pa, Ar 15 sccm). Electrode peeling method: Spin-coat PPC (3000 rpm), prebake 120 °C 2 min, then mechanically peel with tape to separate metal from 2D surface for AFM analysis. Measurement of contact resistance uses transfer length method; Schottky barrier heights are extracted via temperature-dependent measurements (100–300 K).

- A universal, wafer-scale vdW integration using PPC buffer enables damage-free metal contacts to 2D and 3D semiconductors; PPC decomposes cleanly at 250 °C, leaving an atomically sharp interface. - Structural/interface quality: HRTEM shows a vdW gap ~0.3 nm at the WSe2/Au interface. AFM after peeling shows RMS roughness of ~0.16 nm (Cr bottom surface) and ~0.39 nm (WSe2 top surface), indicating clean, flat, residue-free interfaces over large areas. - Wafer-scale demonstration: ~25,000 vdW contacts on a 4-inch wafer in a single batch. - Electrical performance (WSe2, Pd contacts): Both vdW and evaporated contacts show p-type behavior; vdW contact yields on-state current density of ~0.5 µA µm⁻² at Vgs = −60 V, Vds = 1 V, about 7× higher than evaporated Pd contacts. The peak two-point transconductance Gm reaches 1.4 µS (vdW Pd) vs 0.18 µS (evaporated Pd). - Work-function dependence (reduced Fermi level pinning): For vdW contacts across metals (Ag, Ti, Cr, Cu, Co, Au, Pd), higher metal work function leads to larger Ion, higher Ion/Ioff, more positive Vth, and smaller SS, consistent with band alignment. In contrast, evaporated contacts show weak dependence on metal work function, indicating strong pinning. - Contact resistance Rc (Transfer Length Method): vdW Pd ~5.3 kΩ·µm; vdW Au ~10.2 kΩ·µm; vdW Ag ~27.5 MΩ·µm; vdW Ti ~3.9 MΩ·µm. Device performance variations with metal are attributed to Rc changes and transitions between contact-limited and channel-limited regimes. - Schottky barrier heights (extracted 100–300 K): Ag ~116 meV; Ti ~103 meV; Ni ~83 meV; Co ~53 meV; Pd ~36 meV; barrier height scales with metal work function but slope < 1, reflecting residual pinning and p-type nature of CVD WSe2. - Generality: vdW contacts successfully integrated with multiple 2D semiconductors (MoS2, WS2, GeAs, MoTe2) and 3D semiconductors (IGZO, Ge, GaAs, perovskite CsPbX3). For MoTe2 (p-type) and IGZO (n-type), electrical characteristics vary systematically with metal work function under vdW contact, contrasting with weak dependence for evaporated contacts.

The proposed PPC-enabled vdW integration addresses the central challenge of forming clean, low-damage metal contacts to sensitive semiconductors. By interposing and subsequently removing a decomposable polymer, metal deposition no longer perturbs the semiconductor surface, yielding atomically clean interfaces with weak vdW coupling and reduced Fermi level pinning. The observed strong dependence of device metrics (Ion, Ion/Ioff, Vth, SS, Rc, Schottky barrier) on metal work function demonstrates that the contact properties approach Schottky–Mott behavior, a hallmark of minimized pinning. The approach is scalable to wafer level and compatible with industry-relevant, high-adhesion metals that are not amenable to mechanical peeling/transfer methods. Its extension to 3D semiconductors (e.g., IGZO, Ge, GaAs, perovskites) suggests broad applicability for materials that are degraded by high-energy metallization, enabling both low-barrier injection for transistors and high-barrier junctions for Schottky devices. While the current Rc values are not yet at the IRDS targets, the method provides a platform that can be further optimized via dielectric scaling and improved channel quality to unlock higher performance.

This work introduces a scalable, universal vdW metal–semiconductor integration method using a thermally decomposable PPC buffer, enabling atomically clean, damage-free contacts across a wide variety of metals (Ag, Al, Ti, Cr, Ni, Cu, Co, Au, Pd) and semiconductors (2D and 3D). The method avoids manual metal transfer, supports wafer-scale fabrication with high alignment fidelity, and yields contacts with reduced Fermi level pinning, tunable Schottky barriers, and improved device performance. Future directions include: (1) reducing contact resistance via thinner/high-k gate dielectrics and higher-quality channel materials; (2) exploring alternative decomposable buffers (e.g., PPA, polyethylene carbonate, hyperbranched polymers) to tailor processing temperatures and integration windows; (3) expanding to additional semiconductor platforms (organic crystals, other compound semiconductors, halide perovskites) and device architectures (Schottky photodetectors, vertical transistors); and (4) refining lithographic resolutions using advanced stencil techniques for sub-micron contacts.

- The achieved contact resistances (e.g., ~5.3 kΩ·µm for Pd) are higher than best-reported vdW contacts; performance is limited by thick 300 nm SiO2 gate dielectric and channel material quality, suggesting room for optimization. - Despite reduced pinning, the barrier height vs metal work function slope is significantly less than unity; n-type WSe2 behavior was not realized with low-work-function metals, likely due to intrinsic defects and strong p-type doping in CVD WSe2. - Current stencil-mask patterning limits feature size (>10 µm) in the demonstrated process, though sub-micron resolution is possible with improved masks. - The annealing temperature (250 °C) for PPC decomposition may be incompatible with some ultra-thermally sensitive materials, necessitating alternative buffers with lower decomposition temperatures.