Two-dimensional (2D) semiconductors are attractive channel materials for transistors due to their atomically thin bodies and dangling-bond-free surfaces. This offers potential for ultimate body thickness scaling, crucial for mitigating short channel effects and extending Moore's Law. However, creating high-quality metal contacts to 2D semiconductors remains a challenge. Conventional methods (evaporation, sputtering, CVD) are high-energy processes that can damage the delicate 2D materials through kinetic energy transfer or chemical reactions, leading to Fermi level pinning, uncontrollable Schottky barrier heights, and high contact resistance. To address this, low-energy van der Waals (vdW) integration processes have been explored. These involve either low-temperature evaporation of specific metals (In, Bi, Sn) or the mechanical transfer of pre-fabricated metal electrodes. The evaporation method is limited to specific metals with low melting points and questionable thermal stability. The transfer method is hampered by the difficulty of peeling many metals from their substrates, limiting its applicability to a small number of low-adhesion metals. While a Se buffer layer method has been proposed, it still involves high-energy evaporation and its scalability is unexplored. Therefore, a damage-free and scalable vdW integration technique for various 3D metals and 2D semiconductors is needed.

Existing literature extensively details the challenges of creating high-quality metal contacts to 2D semiconductors using conventional high-energy deposition techniques. Studies have demonstrated the significant impact of Fermi level pinning on contact resistance and Schottky barrier height, limiting the performance of 2D transistors. Several approaches have been proposed to mitigate these issues, including the use of low-temperature evaporation of specific metals like indium and the mechanical transfer of pre-fabricated metal electrodes. However, these methods have limitations in terms of the range of applicable metals, scalability, and long-term stability. The use of buffer layers to facilitate vdW contact has also been explored, but with limitations in scalability and potential for damage to the 2D material. This paper builds upon this existing literature by proposing a novel, scalable, and universal approach to vdW metal integration.

The researchers developed a wafer-scale, universal vdW metal integration strategy that utilizes a thermally decomposable poly(propylene carbonate) (PPC) polymer as a buffer layer. The process begins with the synthesis of 2D semiconductors (e.g., WSe2) using chemical vapor deposition (CVD). A 450 nm thick PPC layer is then spin-coated onto the 2D semiconductor. Various metals (60 nm thick) are subsequently deposited onto the PPC layer using standard thermal evaporation. Crucially, the thick PPC layer protects the underlying 2D semiconductor from damage during metal deposition. After metal deposition, the sample undergoes thermal annealing at 250 °C for 30 minutes under a nitrogen atmosphere. This causes the PPC layer to decompose completely into volatile gases, leaving behind a clean vdW interface between the metal and the 2D semiconductor. The process is compatible with industry-standard fabrication techniques and is demonstrated at the wafer scale (4-inch wafer, >25,000 contacts). The quality of the vdW interface was characterized using various techniques including optical microscopy, atomic force microscopy (AFM), scanning electron microscopy (SEM), and high-resolution transmission electron microscopy (HRTEM). AFM was used to assess the interface quality by mechanically peeling off the metal electrodes and analyzing the resulting surfaces. Electrical characterization of WSe2 transistors was performed using various metals as source-drain electrodes, with comparisons made to devices fabricated using conventional evaporation methods. Contact resistance was measured using the transfer length method. The methodology was extended to other 2D semiconductors (MoS2, WS2, MoTe2) and 3D bulk semiconductors (Ge, GaAs, IGZO, perovskite) to demonstrate its universality.

The study successfully demonstrated a wafer-scale vdW metal integration strategy applicable to a wide range of metals and semiconductors. The use of a thermally decomposable PPC buffer layer prevented damage to the underlying semiconductor during metal deposition, yielding atomically clean vdW interfaces. The method enables the integration of high-adhesion metals (e.g., Al, Ti, Cr) that were previously challenging to integrate using existing vdW contact techniques. Detailed characterization techniques confirmed the formation of clean, sharp interfaces. Electrical measurements on WSe2 transistors revealed a strong dependence of electrical performance (on-state current, on/off ratio, threshold voltage, subthreshold swing, transconductance) on the metal work function, indicating a significant reduction in Fermi level pinning compared to devices fabricated using conventional methods. The vdW-contacted devices exhibited significantly higher on-state currents (up to 7 times higher) and transconductance (up to 7 times higher). Contact resistance measurements demonstrated low values for high work function metals (Pd, Au) and higher values for low work function metals (Ag, Ti). The methodology was successfully extended to other 2D and 3D semiconductors, confirming the versatility of the approach and indicating reduced Fermi level pinning as a general trend. The study provides evidence of the effectiveness of this vdW integration strategy in various semiconductor materials.

The findings directly address the research question by demonstrating a scalable and universal method for creating high-quality vdW metal contacts to both 2D and 3D semiconductors. The significant improvement in the electrical performance of vdW-contacted devices compared to conventionally contacted devices highlights the effectiveness of the strategy in minimizing Fermi level pinning. The observed strong dependence of electrical properties on the metal work function is consistent with the theoretical expectations for ideal metal-semiconductor junctions. The successful application of the method to various semiconductor materials demonstrates its broad applicability and potential to impact the development of high-performance electronic and optoelectronic devices. This work represents a major advancement in the field of contact engineering for 2D and 3D semiconductors, paving the way for improved device performance and enabling new possibilities in device design.

This study presents a novel, scalable, and universal method for creating van der Waals contacts between metals and semiconductors. The use of a thermally decomposable polymer buffer layer enables the damage-free integration of a wide range of metals, resulting in significantly improved electrical performance. The successful application of this method to various 2D and 3D semiconductors demonstrates its versatility and potential to advance the development of high-performance devices. Future research could explore the use of alternative buffer materials with different properties to optimize the process for specific semiconductor materials and explore applications in complex device architectures.

While the study demonstrates significant advancements, there are some limitations. The current contact resistance values, while improved, are still higher than some previously reported values for vdW contacts, potentially due to factors such as gate dielectric thickness and channel material quality. The study primarily focuses on p-type semiconductors; further investigations are needed to explore the applicability and effectiveness of this approach for n-type semiconductors. The long channel length used in some devices could also limit the observed current densities, and using shorter channel lengths could further enhance performance.