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Transfer-free rapid growth of 2-inch wafer-scale patterned graphene as transparent conductive electrodes and heat spreaders for GaN LEDs

Engineering and Technology

Transfer-free rapid growth of 2-inch wafer-scale patterned graphene as transparent conductive electrodes and heat spreaders for GaN LEDs

F. Xiong, J. Sun, et al.

Discover a groundbreaking transfer-free technique for growing high-quality patterned graphene directly on GaN LED epilayers, enhancing heat management in devices. This innovative method, developed by Fangzhu Xiong and colleagues, showcases exceptional efficiency and scalability.

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~3 min • Beginner • English
Introduction
Graphene, with high carrier mobility, transmittance, and thermal conductivity, is a promising replacement for indium tin oxide (ITO) as a transparent electrode in GaN LED applications. To avoid complex transfer processes and enable large-scale production, two main approaches exist for growing CVD graphene films directly on GaN: (1) non-catalytic growth at high temperatures, which suffers from quality issues due to lack of a catalyst and lattice mismatch, and can damage GaN through buckling and decomposition; and (2) metal-catalyzed growth where graphene forms on a metal layer on GaN, but removal of the metal typically causes the graphene to float and reintroduces a manual transfer step; keeping the metal degrades transparency. Thus, prior directly grown graphene on GaN has significant limitations. Given GaN’s modest thermal conductivity (125–225 W m−1 K−1) and graphene’s exceptional thermal conductivity (up to ~5300 W m−1 K−1 at room temperature), integrating graphene could also improve heat spreading, which has been rarely reported. To address these challenges, the authors introduce a method that removes the metal catalyst via penetration etching through PMMA and graphene so the graphene naturally falls onto GaN without manual transfer. Co serves both as the catalyst and the GaN mesa dry-etch mask, enabling lithography-free graphene patterning and avoiding photoresist contact with graphene. The approach aims for scalable, low-temperature, rapid, and repeatable wafer-scale graphene integration on GaN LEDs with enhanced electrical and thermal performance.
Literature Review
Prior work on direct, non-catalytic graphene growth on GaN at high temperature demonstrated feasibility but encountered poor film quality and substrate damage due to lattice mismatch and thermal stress. Metal-catalyzed growth routes typically form graphene on the metal atop GaN, but post-growth metal removal causes the graphene to float, effectively reverting to a transfer process; retaining the metal compromises transparency due to metal opacity. Earlier transfer-free attempts using catalytic films (e.g., Ni, Pt) faced challenges in achieving high transparency, easy metal removal, and avoiding resist-induced contamination. Heat spreading benefits of graphene on GaN LEDs have been suggested but were rarely quantified. This study builds on these efforts by using Co as both catalyst and etch mask and employing a penetration etch through PMMA/graphene to eliminate manual transfer while preserving optical/electrical performance.
Methodology
Device fabrication and graphene growth: A 2-inch GaN-on-sapphire LED epiwafer was cleaned. A 300 nm Co layer was deposited and patterned by lift-off lithography and sputtering to define mesa areas. The Co served as a hard mask for inductively coupled plasma (ICP) dry etching to form mesas and expose heavily doped n-GaN. Graphene was then grown on Co by plasma-enhanced CVD (PECVD; Aixtron Black Magic) at 600 °C for 3 minutes using CH4/H2/Ar flows of 5/20/960 sccm and 20 W (15 kHz AC) plasma. Co was selected for its catalytic activity and near-lattice match to graphene. PMMA was spin-coated on the graphene/Co/GaN stack and baked to solidify. Co was removed by penetration etching using CuSO4:HCl:H2O in a 10 g:50 mL:50 mL ratio. The etchant penetrates via graphene grain boundaries/defects and through PMMA’s permeability, enabling smooth Co removal without lifting the graphene. PMMA was then removed with acetone. Finally, p and n electrodes (Ti 20 nm / Au 500 nm) were deposited by sputtering and defined by lift-off. No graphene lithography was required; the graphene pattern followed the Co geometry. Characterization: SEM assessed graphene film uniformity; Raman spectroscopy identified G (1573 cm−1) and 2D (2692 cm−1) peaks and quantified D/G and G/2D ratios; AFM measured roughness for pristine GaN, GaN annealed at 600 °C, and graphene-on-GaN; optical transmittance was measured from 400–1000 nm. Electrical testing included I–V characteristics of LEDs and contact resistance extraction via a circular transfer length model (CTLM). For CTLM, six ring-shaped graphene-on-GaN patterns with 76 μm inner diameter and outer diameters of 84, 90, 96, 106, 113, and 124 μm were fabricated; after annealing at 450 °C, I–V curves between inner and outer graphene rings were measured. Linear fitting of R versus ln(ro/ri) yielded p-GaN sheet resistance and total transmission length; contact resistivity ρc was computed as ρc = Rsh Lt / (π rm). Thermal performance was evaluated at room temperature using SC7300M F/2 (MCT) and Sensing LED-201 systems to determine junction temperature, thermal resistance (K-factor calibration), and temperature maps/line cuts at 20 mA and 100 mA.
Key Findings
- Rapid, low-temperature, transfer-free graphene: PECVD growth at 600 °C for 3 min on Co patterned atop GaN, followed by penetration etch through PMMA/graphene to remove Co, leaving graphene directly on p-GaN with lithography-free patterning. - Graphene film quality: Raman G at 1573 cm−1 and 2D at 2692 cm−1; D/G = 0.28; G/2D = 1.99; Raman mapping over 40 μm × 40 μm confirms uniform quality. AFM roughness: pristine GaN 0.228 nm; GaN annealed at 600 °C 0.848 nm; graphene-on-GaN 0.604 nm. Average optical transmittance ~89.84% (400–1000 nm). Sheet resistance 631.2–868 Ω sq−1 (as low as 631.2 Ω sq−1). - Contact to p-GaN: CTLM-derived contact resistivity ρc = 0.421 Ω cm² after 450 °C anneal; better than typical contacts with transferred graphene, though still higher than ITO. - LED electrical and optical performance: At 20 mA, graphene-coated LED operates at 5.54 V vs 6.59 V for pristine GaN LED. Luminous flux higher by ~6% at 20 mA and ~18% at 100 mA. Radiation flux: 2.884 mW (graphene-coated) vs 2.2 mW (pristine) at 20 mA (+31%); 6.210 mW vs 5.053 mW at 100 mA (+23%). EL FWHM narrowed by 3.2 nm (20 mA) and 5.8 nm (100 mA). Uniform emission across p-GaN area; device success rate >90% with nearly 100% graphene integrity pre-liftoff. - Thermal performance: At 2 mA, junction temperature and thermal resistance: graphene-coated 40.25 °C and 42.25 °C W−1 (K-factor ~0.64 mV °C−1); pristine 63.61 °C and 85.8 °C W−1 (K ~2.35 mV °C−1). Temperature rise along device at 20 mA similar for both (graphene-coated ~0.61–1.36 °C; pristine ~0.62–1.25 °C), but at 100 mA graphene-coated shows lower rise (~9.05–11.93 °C) than pristine (~11.43–16.5 °C), indicating superior heat spreading by graphene.
Discussion
The study addresses key barriers to integrating graphene transparent electrodes on GaN LEDs by eliminating manual transfer and resist exposure, thus avoiding wrinkles, tears, and contamination. Using Co as both mesa etch mask and graphene growth catalyst enables lithography-free graphene patterning aligned to device mesas, streamlining fabrication and enhancing compatibility with semiconductor processes. The penetration etch through PMMA/graphene removes Co without lifting or damaging graphene, producing intact wafer-scale arrays. Experimentally, the graphene electrodes provide low sheet resistance with high optical transmittance and establish in-situ ohmic contact to p-GaN with moderate contact resistivity. Device-level comparisons show reduced forward voltage at a given current, increased luminous and radiation flux, and narrowed EL spectra, evidencing improved current spreading and optical output. Thermal characterizations demonstrate lowered junction temperature and thermal resistance, and reduced temperature rise at high current, validating graphene’s role as an effective heat spreader on GaN LEDs. Collectively, these results confirm that the proposed transfer-free integration enhances both electrical and thermal performance while offering a scalable and industry-compatible path for wafer-scale device fabrication.
Conclusion
This work demonstrates a transfer-free, wafer-scale method to integrate patterned graphene directly on GaN LEDs using Co as both a PECVD growth catalyst and a mesa etch mask, followed by penetration etching through PMMA/graphene to remove Co. The resulting graphene exhibits high transparency (~90%), low sheet resistance (~631–868 Ω/sq), and forms in-situ ohmic contact to p-GaN (ρc ~0.421 Ω cm²). LEDs with graphene electrodes show lower operating voltage, increased luminous and radiation flux, narrower EL FWHM, and improved thermal performance (lower junction temperature and thermal resistance) compared to graphene-free devices. The approach avoids transfer-related defects and is inherently scalable and compatible with standard semiconductor processes. Potential future directions include: optimization of contact resistivity toward ITO-level performance, controlled doping to further reduce graphene sheet resistance, scaling to larger wafer sizes with appropriate equipment, and extending the penetration-etch, transfer-free concept to other 2D materials and device platforms.
Limitations
- The measured graphene–p-GaN contact resistivity (0.421 Ω cm²) remains higher than state-of-the-art ITO contacts. - CTLM measurements omitted additional metal electrodes to avoid ambiguity, which may lead to overestimation or variability due to probe–graphene contact quality. - Some graphene damage can occur during lift-off of patterned metal electrodes due to variable resist–graphene adhesion, slightly reducing device yield (though overall success rate remains >90%). - Sample size and wafer-scale demonstrations are limited by PECVD heater and chamber dimensions; larger-scale validation requires appropriate equipment. - Sheet resistance, while relatively low, could benefit from doping or further process optimization to reach lower values for high-current applications.
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