Neuromorphic hardware utilizing memristive synapses offers energy-efficient data processing for AI and machine learning. The core of this efficiency lies in the in-memory computation of vector-matrix multiplications (VMMs) within neural networks. Weights are non-volatilley stored in the memristive synapses, and inference involves applying small voltages and reading the output currents. Multiply-accumulate (MAC) operations are directly executed via Ohm's and Kirchhoff's laws, eliminating the energy-intensive data movement inherent in von Neumann architectures. This parallel, in-memory, and analog computation results in significant improvements in energy efficiency and throughput. However, memristive synapses must meet specific requirements for both inference (retention, multilevel states, 3D stackability, high resistance to avoid excessive current) and learning (linear and symmetric programming). Two-terminal memristive devices are attractive due to their area efficiency but often suffer from reliability issues, particularly variability. This variability, stemming from stochastic ion migration in resistive switching memories, degrades performance. Ferroelectric (FE) polarization switching offers a potential solution due to its inherent stability and non-filamentary nature. Ferroelectric tunnel junctions (FTJs) are particularly promising candidates due to their non-filamentary nature, high endurance, high resistance, and low current. However, FTJs present challenges: their nonlinear and asymmetric weight updating behavior under identical pulses due to FE polarization switching kinetics. While incremental step pulses (ISPs) help mitigate this nonlinearity, they are not fully effective. Previous approaches, such as the two-transistor-one-ferroelectric field-effect transistor (FeFET) synapse and modifying the FE layer's microstructure, have yielded improvements but come with area overhead or increased programming voltage. This work introduces a novel artificial synapse architecture using multiple parallel FTJs to improve linearity and minimize variability.

The literature review extensively covers existing memristive devices used in neuromorphic computing, highlighting the challenges and limitations of resistive switching memories (RRAMs), spintronic memories, phase-change memories, and FE-based devices. The authors discuss the advantages and disadvantages of each technology, focusing on issues like variability, linearity, and energy efficiency. They specifically analyze previous attempts to address the nonlinearity issue in FTJs, including the use of ISPs, the 2T-1FeFET approach, and FE microstructure modifications. These previous solutions were shown to have tradeoffs such as increased device complexity, larger area, or limitations in linearity and symmetry. The review sets the stage for the authors' proposed approach, positioning it as an improvement upon existing techniques by mitigating the nonlinearity of FTJs without significant drawbacks. The lack of significant variability in their FTJs differentiates their work, setting it apart from the previous research in the field.

The FTJs were fabricated on a highly doped p-type 8-inch silicon wafer. After cleaning and ozone pretreatment, a 50 nm TiN bottom electrode was sputtered, followed by the deposition of a 4 nm (Hf,Zr)O2 FE layer via thermal atomic layer deposition (ALD) at 300 °C. A 50 nm Mo top electrode was sputtered, and rapid thermal annealing at 500 °C crystallized the FE layer. Top electrode sizes varied from 400 to 10,000 µm². Electrical measurements were performed using a semi-auto probe station with a Keithley SCS4200, employing PUND measurements for FE hysteresis curves and DC current-voltage measurements to assess conductance change and reliability. A customized pulse-write and DC-read protocol characterized long-term potentiation and depression (LTPD). The key aspect of the methodology is the parallel arrangement of FTJs within a single synapse. Multiple FTJs share the same access transistor, but each has its own plate line (PL) with different offset biases. This design ensures that when a programming pulse is applied, each FTJ operates on a different portion of its switching curve, effectively averaging the nonlinear behavior. The switching reproducibility and wafer-level uniformity of individual FTJs were crucial, requiring 1000 cycles of wake-up pulses and a PUND measurement to confirm ferroelectric properties. DC current-voltage measurements were performed to evaluate area independence, endurance, and retention. Statistical analysis, including calculations of mean-to-deviation ratios (σ/µ), was conducted on the data to quantify variability.

The study achieved extremely low variability in the fabricated FTJs. Cycle-to-cycle (C2C) variability (σ/µ) was 0.036, and device-to-device (D2D) variability was 0.032 across six dies on an 8-inch wafer. The area-independent current density demonstrated the robustness of the FTJ's FE properties. The parallel FTJ synapse design successfully mitigated the nonlinearity inherent in individual FTJs. Nonlinearity (α) improved from -3.25/-2.51 (single FTJ) to -0.18/-1.14 (four parallel FTJs) for potentiation/depression, respectively. This design resulted in a 96.84% pattern recognition accuracy in MNIST dataset simulations, approaching the software limit of 97.26%. The average energy consumption per programming pulse was 130.1 fJ µm⁻², and the maximum read power consumption was 146 fW µm⁻². The superior performance was validated by comparison to other reported two-terminal and three-terminal devices, showing significant advantages in nonlinearity, asymmetry, and variability while maintaining low operation voltages.

The findings demonstrate the efficacy of the proposed parallel FTJ synapse design for neuromorphic computing. The exceptionally low variability achieved in the FTJs is a crucial advancement, addressing a major limitation of previous memristive devices. The improvement in linearity significantly enhances the accuracy of neural network training and inference. The demonstrated high pattern recognition accuracy using the MNIST dataset validates the practical applicability of the design. The low energy consumption and operation voltage make it a promising solution for energy-efficient edge AI applications. The results suggest that the parallel FTJ design can overcome the intrinsic limitations of individual FTJs, creating a more reliable and efficient synaptic device for neuromorphic hardware. This work significantly contributes to the field by providing a practical solution to the linearity and variability issues associated with FE-based synapses, paving the way for large-scale deployment of neuromorphic computing systems.

This paper presents a novel synaptic design employing parallel FTJs for neuromorphic computing. The design mitigates the nonlinear weight update behavior of individual FTJs through averaging the switching rates of multiple devices with different pulse amplitude ranges. Extremely low device variability (σ/µ = 0.036 for C2C and 0.032 for D2D) was achieved, contributing to improved accuracy (96.84% on MNIST). The parallel architecture is scalable and compatible with 3D integration, making it highly promising for building efficient and accurate neuromorphic hardware. Future work could focus on optimizing the conductance of FTJs and exploring different FE materials for enhanced performance.

The current study focuses on simulation results using a small neural network architecture. While the results are promising, further research is needed to validate the performance on larger, more complex networks and real-world datasets. The study primarily uses MNIST datasets; other datasets that explore different types of image and data patterns should be used for further validation. The demonstrated parallel FTJ synapse operates at a relatively low conductance, which may need to be improved to optimize the speed and accuracy of computations. While the 3D integration is conceptually illustrated, its experimental implementation remains a future challenge. A thorough long-term reliability study of the parallel FTJ synapses with extended testing is needed to confirm device lifetime and endurance under real-world operating conditions.