Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing

We propose a novel synaptic design of more efficient neuromorphic edge-computing with substantially improved linearity and extremely low variability. Specifically, a parallel arrangement of ferroelectric tunnel junctions (FTJ) with an incremental pulsing scheme provides a great improvement in linearity for synaptic weight updating by averaging weight update rates of multiple devices. To enable such design with FTJ building blocks, we have demonstrated the lowest reported variability: σ/µ = 0.036 for cycle to cycle and σ/µ = 0.032 for device among six dies across an 8 inch wafer. With such devices, we further show improved synaptic performance and pattern recognition accuracy through experiments combined with simulations.

Taehwan Moon, Hyun Jae Lee, Seunggeol Nam, Hagyoul Bae, Duk-Hyun Choe, Sanghyun Jo, Yun Seong Lee, Yoonsang Park, J Joshua Yang, Jinseong Heo