Two-dimensional (2D) van der Waals (vdW) materials, particularly transition metal dichalcogenides (TMDCs) like molybdenum disulfide (MoS₂), are promising for next-generation electronics due to their unique properties such as high electron mobility, tunable bandgap, and ease of integration. Heterostructures built from stacked 2D materials offer diverse device architectures, including dual-gate FETs and split-gate FETs (SG-FETs). SG-FETs, with sequentially located split gates along the source/drain electrodes, provide local control over carrier concentration. Logic circuit applications, requiring at least two transistors for gates like AND, OR, NAND, and NOR, are crucial for demonstrating advanced electronic performance. Previous research has used dual-gate and SG-FETs to implement these logic gates within a single active channel. This study aims to demonstrate single MoS₂-based NAND and NOR logic gates using different SG-FET structures, where the gap direction of the split gates (longitudinal or latitudinal to the channel) determines the switching characteristics (AND or OR). This approach is expected to significantly improve the functionality and integration density of 2D material-based electronics.

The literature extensively covers the use of 2D vdW materials, especially TMDCs, in field-effect transistor (FET) applications. Monolayer MoS₂ has demonstrated high electron mobility and ON/OFF current ratios, making it a suitable active channel material. Heterostructure devices, created by stacking different 2D materials, have been explored for dual-gate FETs, tunnel FETs (TFETs), and SG-FETs. SG-FETs offer advantages in device integration and the creation of novel logic devices. Prior work demonstrated the use of dual-gate FETs and SG-FETs to realize conventional logic gates using a single active channel, showcasing the high functionality and integration potential of 2D materials. This research builds on these previous findings by exploring the impact of gate geometry on logic function within a single MoS₂ channel.

The fabrication process began with ultrasonic cleaning of a glass substrate. Graphene source/drain electrodes, MoS₂ active channel, and hexagonal boron nitride (h-BN) top-gate insulator were exfoliated and transferred onto the substrate using polydimethylsiloxane (PDMS) stamps. Platinum/Titanium/Platinum (Pt/Ti/Pt) tri-layered electrodes were deposited using DC sputtering, defined by photolithography and lift-off processes. The nano-gapped split gate structures were created using a nanogap patterning technique (details in Supplementary Fig. 1 and 2). The AND-FET had sequentially located split gates along the source/drain direction, while the OR-FET had split gates perpendicular to this direction. Static electrical measurements, including I_D-V_G transfer characteristics, I_D-V_O output characteristics, mapped I_O plots, and voltage transfer characteristics (VTCs), were performed using an Agilent 4156B semiconductor parameter analyzer and a Tektronix AFG 1062 function generator at room temperature in a dark box.

The AND-FET, with longitudinally arranged split gates, showed four distinct transition modes (AA, DD, DA, AD) depending on the first and second gate voltages (V_G1 and V_G2). High drain current (I_D) was observed only in the AA mode (both gates in accumulation), demonstrating AND switching characteristics. The device behaved as a quasi-single gate FET when a common gate voltage was applied. The AND-FET's operation is analogous to a series connection of two n-type transistors. The OR-FET, with laterally arranged split gates, also exhibited four transition modes. High I_D was observed in AA, DA, and AD modes, signifying OR switching characteristics with a low I_D only in the DD mode (both gates in depletion). This behavior resembles a parallel connection of two n-type transistors. Inverter circuit applications were implemented using both AND-FET and OR-FET. The AND-FET-based inverter demonstrated NAND logic, while the OR-FET-based inverter exhibited NOR logic, both using a single MoS₂ active channel. The truth tables for both NAND and NOR logic were experimentally verified.

The successful demonstration of NAND and NOR logic gates using a single MoS₂ active channel with structurally engineered split-gate FETs highlights the potential of 2D materials for high-density, multifunctional integrated circuits. The observed AND and OR switching characteristics, determined solely by the split-gate electrode arrangement, represent a significant advancement in 2D material device design. The results confirm the feasibility of creating complex logic functions with a greatly reduced transistor count compared to conventional approaches. The independent control of carrier concentration in different regions of the MoS₂ channel, achieved by the split-gate configuration, is key to this functionality. This work lays a foundation for exploring more sophisticated logic operations and reconfigurable devices based on similar structural engineering of split-gate architectures.

This study successfully demonstrated the implementation of NAND and NOR logic gates using two distinct split-gate MoS₂ field-effect transistors. The AND-FET and OR-FET, differing only in split-gate arrangement, exhibited AND and OR switching characteristics, respectively. This approach enabled NAND and NOR logic operations within a single MoS₂ active channel, significantly enhancing the integration density and functionality of 2D material-based electronics. Future research could explore more complex multi-value logic and reconfigurable devices using this approach.

The current study focuses on demonstrating the basic principle of using different split-gate geometries to achieve specific logic functions. Further research is needed to optimize the device performance, such as improving the ON/OFF ratio and reducing leakage currents, for practical applications. The scalability and manufacturability of the nano-gap patterning technique also need further investigation for large-scale integration.