Longitudinal and latitudinal split-gate field-effect transistors for NAND and NOR logic circuit applications

Two-dimensional van der Waals (2D vdW) materials, consisting of atomically thin bodies and dangling-bond-free surfaces, have attracted significant research interest for the development of future electronics and their applications. Transition metal dichalcogenide (TMDC) semiconductors have emerged as active channel materials owing to their outstanding electrical properties, with monolayer MoS₂ demonstrating high electron mobility and high ON/OFF ratios. The tunable bandgap of MoS₂ (from ~1.3 eV in bulk to ~1.9 eV in monolayer) overcomes limitations of gapless graphene. Heterostructure devices built by stacking different 2D vdW materials enable diverse device architectures such as dual-gate FETs, TFETs, heterojunctions, and split-gate FETs (SG-FETs). Dual-gate FETs modulate channels from top and bottom, whereas SG-FETs employ two sequential gates along the source/drain to locally control carrier concentration, offering strengths in integration and new logic functionalities. Conventional logic gates (AND, OR, NAND, NOR) typically require at least two transistors; series n-FETs implement NAND and parallel n-FETs implement NOR in pull-down networks. Prior works have realized such gates with single channels using dual-gate or split-gate devices. In this study, the authors demonstrate single MoS₂-based NAND and NOR logic gates realized by two SG-FET structures whose split-gate gap directions are longitudinal (AND-FET) or latitudinal (OR-FET) relative to the channel. Because the gap directions are perpendicular, the devices exhibit different switching characteristics (AND vs OR). This structural engineering targets increased functionality and integration in 2D electronics.

Prior research established high-performance MoS₂ FETs with high mobility and ON/OFF ratios, and explored vdW heterostructure devices including dual-gate FETs, TFETs, and SG-FETs. Dual-gate and SG-FET architectures have previously demonstrated conventional logic with single active channels, indicating the potential for compact, multifunctional circuits. Graphene contacts can improve ON/OFF behavior via Fermi level modulation. Recent works also advanced reconfigurable and polarity-controllable 2D transistors and compact logic with minimal device counts. Building on these, the present work focuses on how the orientation of the split-gate gap in homogeneous MoS₂ SG-FETs determines AND or OR switching behavior, enabling NAND/NOR with a single channel.

Device structure and fabrication: Devices were built on glass substrates cleaned ultrasonically in acetone, methyl alcohol, and isopropyl alcohol for 15 min each. Graphene source/drain (S/D), MoS₂ active channel, and h-BN top-gate insulator were exfoliated and transferred using PDMS stamps to form the device stack. Zinc-oxide (ZnO) nanowires (NWs), grown separately, were dispersed onto PDMS by a drop-and-dry method with IPA and transferred to target sites atop the h-BN/MoS₂ platform. Pt/Ti/Pt (20/10/20 nm) tri-layer electrodes were deposited by DC sputtering on photolithographically defined patterns, followed by lift-off. The attached ZnO NWs beneath the monolithic gate electrodes were mechanically removed to create nanogaps, realizing top-gate staggered MoS₂ split-gate FETs with nano-gapped gate electrodes. Two SG-FET configurations were fabricated: AND-FET with the split-gate gap oriented longitudinally along the channel (sequential SGs along S/D), and OR-FET with the gap oriented latitudinally (side-by-side SGs across the channel width). Both used graphene S/D, MoS₂ channel, and h-BN gate dielectric. A nanogap patterning technique defined the nanoscale split between Gate1 (G1) and Gate2 (G2), and ensured electrical isolation of the two inputs. Electrical characterization: Static electrical measurements, including ID–VG transfers, ID–VD outputs, 2D maps of ID versus (VG1, VG2), and inverter voltage transfer characteristics (VTCs), were performed using an Agilent 4156B semiconductor parameter analyzer and a Tektronix AFG1062 function generator in a dark box at room temperature. For AND-FET mapping, VG1 and VG2 were swept from −7 to 7 V at VD = 1 V. For OR-FET mapping, VG1 and VG2 were swept from −3 to 3 V at VD = 3 V. Common-gate operation was also evaluated by tying G1 and G2 together. Inverter tests used external resistors per the provided circuit diagrams, with Vin1 and Vin2 applied to G1 and G2, respectively, and Vout measured across the load at specified VDD.

- Orientation-controlled switching: The longitudinal-gap SG-FET (AND-FET) exhibits AND switching, with high ID only when both gates are high (AA mode). The latitudinal-gap SG-FET (OR-FET) exhibits OR switching, with high ID when either or both gates are high (AA, AD, DA), and low ID only when both are low (DD). - Bias ranges and modes: AND-FET mapping over VG1, VG2 ∈ [−7, 7] V at VD = 1 V shows four modes (AA, AD, DA, DD), with high ID only in AA; all other modes yield low ID. OR-FET mapping over VG1, VG2 ∈ [−3, 3] V at VD = 3 V shows high ID in AA, AD, and DA, and low ID in DD. - Mechanisms: In AND-FET, sequential gates along the channel allow independent formation/depletion in two series channel segments; any depletion breaks the current path (series-equivalent behavior). In OR-FET, side-by-side gates form two parallel conduction paths across the channel width; any one conducting path yields high ID (parallel-equivalent behavior). In OR-FET, ID(AA) ≈ ID(AD) + ID(DA), evidencing two independent current paths; DA current exceeded AD due to wider MoS₂ under G2. - Common-gate operation: Tying G1 and G2 produces quasi-single-gate MoS₂ FET behavior with high ON/OFF, attributed to graphene S/D Fermi level modulation improving both ON and OFF currents relative to metal S/D of similar work function. - Logic demonstrations: Using a single MoS₂ channel device in an inverter configuration, the AND-FET implements NAND logic (only output 0 at input (1,1)) with VDD = 1 V and Vin sweeps of −7 to 7 V. The OR-FET implements NOR logic (only output 1 at input (0,0)) with VDD = 3 V and Vin sweeps of −3 to 3 V. Time-domain measurements confirmed the truth tables. - Integration benefit: NAND and NOR gates were realized using a single active channel each, effectively halving the transistor count versus conventional series/parallel networks.

The study addresses whether the orientation of the split-gate gap in a homogeneous MoS₂ SG-FET can dictate logic switching behavior and enable complex logic with a single channel. The longitudinal (along-channel) split-gate yields series-like segmentation of the channel, producing AND switching (current flows only if both segments are accumulated). The latitudinal (across-channel) split-gate yields two parallel conduction paths, producing OR switching (current flows if either path is accumulated). These behaviors directly translate to NAND and NOR when the devices are used as pull-down elements in resistor-loaded inverters, confirmed by VTCs and time-domain truth tables. The results underscore how simple structural engineering of SG orientation in 2D FETs can achieve multifunctional logic while improving integration density. Additionally, common-gate tests highlight the advantage of graphene S/D contacts via Fermi level modulation, reinforcing device performance and ON/OFF control. The distinct current additivity in OR-FET (ID(AA) ≈ ID(AD) + ID(DA)) and interruption in AND-FET validate the proposed operating mechanisms and their equivalence to folded parallel/series networks of two n-type transistors.

The work demonstrates two MoS₂-based SG-FET architectures whose split-gate gap orientations control logic behavior: longitudinal-gap AND-FET (series-equivalent) and latitudinal-gap OR-FET (parallel-equivalent). Both achieve robust AND/OR switching across defined gate voltage ranges and enable single-channel implementations of NAND and NOR logic gates in inverter configurations, reducing device count and enhancing integration. The approach provides a simple structural route to multifunctionality in 2D electronics. The authors suggest extensions to advanced logic, including multi-valued logic via asymmetric OR-FET designs and reconfigurable characteristics using both top and bottom split gates for neuromorphic applications.