Interface engineering for substantial performance enhancement in epitaxial all-perovskite oxide capacitors

Dynamic random access memory (DRAM) operation requires a certain level of charge-storage capacity. With developments in DRAM generation, the thickness of capacitors should decrease to satisfy the high-aspect-ratio requirement established by the design rule for DRAM capacitors. However, this scaling down of capacitors limits their charge-storage capability. Therefore, the properties of the thin dielectric layer must be enhanced and optimized. To overcome these problems, investigations on metal-insulator-metal (MIM) capacitors must be conducted to leverage their high dielectric permittivity (κ) values and thin dielectric layers. Because increasing the permittivity of the dielectric in an ultrathin capacitor can offset the aforementioned charge-storage limitations, ternary perovskite oxides that exhibit higher dielectric permittivity values than ZrO2 and HfO2, which are currently used in DRAM capacitors, have attracted research attention. In particular, SrTiO3 and doped SrTiO3 are representative ternary perovskite oxide materials; SrTiO3 exhibits general dielectric characteristics, whereas Ba-doped SrTiO3, a representative relaxor ferroelectric material, shows extremely high dielectric permittivity at the ferroelectric-to-paraelectric transition temperature. SrTiO3 shows paraelectric properties and has no transition temperature that shows a transition in dielectric properties. However, Ba-doped SrTiO3 substituted with Ba instead of Sr at the A-sites of SrTiO3 shows a ferroelectric-to-paraelectric transition. The transition temperature increases with increasing amounts of doped Ba. Therefore, a high dielectric permittivity can be achieved with Ba-doped SrTiO3 at a desired temperature by controlling the Ba concentration. In the dielectric layer, carriers can be transferred via two mechanisms: material-property-induced and defect-induced carrier conduction. Material property-induced carrier conduction includes Schottky emission and direct tunneling, which occur when the bandgap of the dielectric is narrow and when the dielectric is extremely thin, respectively. Defect-induced carrier conduction includes Poole-Frenkel (P-F) emission and hopping conduction, which are caused by defects acting as trap sites in the dielectric layer. Both mechanisms, which are caused by material properties and defects in the dielectric layer, affect the leakage current and are simultaneously activated. Therefore, as the thickness of SrTiO3 or Ba-doped SrTiO3 with a narrow bandgap (3 eV) decreases, the defects in the dielectric layer increase the leakage current and suppress the ultimate dielectric properties. To overcome these limitations caused by the leakage current in Ba-doped SrTiO3, investigations of high-performance capacitors with defect control imparted via interface engineering must be prioritized. In this study, the leakage behavior and defect-formation mechanism of a SrRuO3/Ba0.5Sr0.5TiO3/SrRuO3 capacitor were investigated through precisely controlled interfacial engineering by using an ultrathin epitaxial scheme to fabricate a 10 nm-thick dielectric layer.

Thin film growth: All perovskite oxide layers were grown by pulsed laser deposition (PLD) using a KrF excimer laser (λ = 248 nm). Prior to film growth, a SrTiO3 (100) single-crystal substrate was etched with a buffered hydrofluoric acid etchant and annealed at 1000 °C for 1 h to form a Ti-terminated surface. SrRuO3 and Ba0.5Sr0.5TiO3 perovskite oxides were grown in an oxygen atmosphere at a working pressure of 100 mTorr. During PLD, the substrate temperature was maintained at 700 °C. The thicknesses of the bottom electrode, dielectric layer, and top electrode were fixed at 30, 10, and 50 nm, respectively. To engineer the interface between the bottom electrode and the dielectric layer, SrRuO3 bottom electrodes were grown with repetition frequencies of 2, 5, and 10 Hz. Subsequently, the Ba0.5Sr0.5TiO3 dielectric layer and SrRuO3 top electrode were grown at an identical frequency of 10 Hz.

Structural and electrical characterization: AFM, XRD, and the Van der Pauw method were employed to confirm that the SrRuO3 bottom electrodes fabricated at different repetition frequencies were of high quality. The microstructure of the epitaxially grown SrRuO3/Ba0.5Sr0.5TiO3/SrRuO3 capacitor was characterized by cross-sectional HAADF-STEM. The engineered interface between the SrRuO3 bottom electrode and Ba0.5Sr0.5TiO3 was analyzed by HAADF intensity profiling. All top SrRuO3 electrodes were defined by patterning with a Ti/Pt hard mask. Temperature-dependent C–V and I–V characteristics were determined using a probe station with a grounded bottom electrode and a biased top electrode.

Band structure predictions (DFT): Density functional theory calculations were performed with VASP using PAW potentials and the PBE exchange-correlation functional. A Hubbard U correction (GGA+U) with U = 4.0 eV was applied to Ti d electrons. The plane-wave energy cutoff was 600 eV. A 3×3×3 SrTiO3 supercell (cubic perovskite) and a 3×3×3 Monkhorst–Pack k-point mesh were used. The supercell was fully relaxed (force convergence 0.001 eV/Å), giving a lattice constant a = 3.904 Å. Four defect configurations were modeled: oxygen vacancy (VO), Ru substitution on Sr site (RuSr), and two coexisting VO+Ru cases with distant (≈5.856 Å) and adjacent (≈1.952 Å) separations. Defected supercells were relaxed at fixed volume. Spin-polarized DOS were computed to analyze defect-induced in-gap states.

• Interface engineering via lowering the PLD repetition frequency for the SrRuO3 bottom electrode produced an atomically smooth, pit-free, and more stoichiometric surface, suppressing interfacial defect formation and Ru diffusion into Ba0.5Sr0.5TiO3.
• HAADF-STEM/FFT confirmed epitaxial growth in all samples; HAADF intensity profiling revealed B-site (Ti/Ru) intensity slopes spanning ~3 unit cells at 10 Hz, reduced to 1–2 unit cells at 5 Hz, and eliminated at 2 Hz, consistent with reduced interdiffusion and pit formation at lower frequencies.
• Electrical performance improved markedly with reduced bottom-electrode repetition frequency. While κmax slightly decreased from 931 (10 Hz) to 861 (2 Hz), dissipation factors dropped by >1 order of magnitude, and leakage current density J@1 V decreased by ~4 orders of magnitude from 4.28×10^-2 A/cm^2 (10 Hz) to 5.15×10^-6 A/cm^2 (2 Hz) for a 10 nm dielectric.
• UPS showed identical SrRuO3 work functions (5.1 eV) across growth conditions, excluding Schottky emission changes; temperature-dependent I–V fits indicated Poole–Frenkel (P–F) emission in 5/10 Hz samples but hopping conduction in the 2 Hz sample.
• DFT DOS analyses showed: VO and Ru substitution each introduce deep in-gap states; when VO is adjacent to substituted Ru, shallow in-gap states just below the conduction band arise, serving as P–F trap sites. Reduced interfacial roughness and Ru diffusion at 2 Hz mitigates formation of adjacent VO–Ru complexes, suppressing P–F conduction.
• The best device (2 Hz bottom electrode) achieved κ ≈ 861 and J@1 V ≈ 5.15×10^-6 A/cm^2 with a 10 nm Ba0.5Sr0.5TiO3 layer, yielding excellent equivalent oxide thickness (EOT) and leakage compared with prior SrRuO3-based perovskite capacitors.

The study addresses the central challenge of high leakage in ultrathin perovskite-oxide capacitors with narrow bandgap dielectrics by engineering the dielectric/electrode interface. Lowering the PLD repetition frequency for the SrRuO3 bottom electrode reduces surface pits and Ru deficiency, thereby minimizing interfacial interdiffusion (notably Ru into the Ba0.5Sr0.5TiO3 B-site) and the formation of defect complexes. Structural profiling (HAADF) links reduced B-site intensity gradients to smoother, chemically sharper interfaces. Identical electrode work functions across conditions indicate that the dominant changes in leakage arise from defect-related mechanisms rather than barrier height variations. Temperature-dependent transport reveals a transition from Poole–Frenkel emission (5/10 Hz) to hopping conduction (2 Hz), consistent with a reduction of shallow trap states near the conduction band. DFT supports this mechanism by showing that adjacent oxygen vacancy–Ru substitution complexes create shallow in-gap states that facilitate P–F conduction, whereas suppressing such complexes limits these traps. Consequently, the engineered interface enables both low leakage (5.15×10^-6 A/cm^2 at 1 V) and high dielectric permittivity (κ ≈ 861) in a 10 nm Ba0.5Sr0.5TiO3 layer, advancing the feasibility of all-perovskite MIM capacitors for DRAM where aggressive scaling and high capacitance are required.

This work demonstrates that precise interface engineering of epitaxial SrRuO3/Ba0.5Sr0.5TiO3/SrRuO3 MIM capacitors—achieved by reducing the PLD repetition frequency for the SrRuO3 bottom electrode—suppresses interfacial defects and Ru diffusion, thereby mitigating shallow trap formation responsible for Poole–Frenkel leakage. The optimized device with a 10 nm dielectric achieves κ ≈ 861 and J@1 V ≈ 5.15×10^-6 A/cm^2, representing substantial performance with one of the thinnest reported dielectric layers for such systems. The combined experimental transport analyses and DFT DOS calculations elucidate the defect mechanisms, offering a clear pathway to further reduce leakage in narrow-bandgap perovskite dielectrics. These findings pave the way for integrating high-κ perovskite oxides into next-generation DRAM capacitors requiring ultrathin, high-capacitance dielectrics.