Dynamic Random Access Memory (DRAM) requires significant charge storage capacity. As DRAM generations advance, capacitor thickness must decrease to meet high-aspect-ratio design rule requirements. However, this scaling reduces charge storage, necessitating enhanced thin dielectric layer properties. Metal-insulator-metal (MIM) capacitors, with their high dielectric permittivity (κ), offer a solution. Ternary perovskite oxides, such as SrTiO₃ and Ba-doped SrTiO₃, exhibit higher permittivity than currently used ZrO₂ and HfO₂, making them attractive. Ba-doped SrTiO₃, a relaxor ferroelectric material, shows extremely high permittivity near its ferroelectric-to-paraelectric transition temperature. However, undoped SrTiO₃, being paraelectric, lacks this transition. The leakage current in these materials, particularly with thin layers, is a major concern. Carriers can be transported through material-property-induced mechanisms (Schottky emission and direct tunneling) and defect-induced mechanisms (Poole-Frenkel emission and hopping conduction). Reducing the leakage current through defect control via interface engineering is crucial for high-performance capacitors. This study investigates the leakage behavior and defect formation mechanisms in a SrRuO₃/Ba₀·₅Sr₀·₅TiO₃/SrRuO₃ capacitor using an ultrathin epitaxial approach to create a 10 nm thick dielectric layer and carefully engineered interfaces.

The literature extensively covers perovskite oxides for DRAM capacitors, highlighting their potential for high dielectric permittivity. Studies have focused on SrTiO₃ and its Ba-doped variants due to their superior dielectric properties compared to conventional materials like ZrO₂ and HfO₂. However, challenges arise from the narrow bandgap of these materials, which leads to high leakage current density, particularly in ultrathin films. Previous research has explored various strategies to mitigate leakage, such as doping and defect engineering. This study builds upon this existing work, focusing on precise interface engineering to minimize defect formation and enhance capacitor performance.

Perovskite oxide layers were grown using pulsed laser deposition (PLD) with a KrF excimer laser (λ= 248 nm). A SrTiO₃ (100) single-crystal substrate, after etching and annealing, served as the base. SrRuO₃ and Ba₀·₅Sr₀·₅TiO₃ were deposited in an oxygen atmosphere (100 mTorr) at 700 °C. The bottom electrode, dielectric layer, and top electrode thicknesses were 30 nm, 10 nm, and 50 nm, respectively. Interface engineering was achieved by varying the SrRuO₃ bottom electrode growth repetition frequency (2, 5, and 10 Hz). The Ba₀·₅Sr₀·₅TiO₃ dielectric layer and SrRuO₃ top electrode were grown at 10 Hz. Atomic force microscopy (AFM), X-ray diffraction (XRD), and the Van der Pauw method characterized the SrRuO₃ bottom electrodes. Cross-sectional high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) analyzed the capacitor microstructure and interface. The top SrRuO₃ electrodes were patterned using a Ti/Pt hard mask. Temperature-dependent capacitance-voltage (C-V) and current-voltage (I-V) characteristics were measured. Density functional theory (DFT) calculations, using the Vienna Ab Initio Simulation Package (VASP) with the Perdew-Burke-Ernzerhof exchange-correlation functional and Hubbard-U correction, were performed to understand the electronic structure and defect effects. Various defects (oxygen vacancies, Ru substitution, and combinations thereof) were modeled in a 3 x 3 x 3 SrTiO₃ supercell.

AFM revealed that SrRuO₃ grown at higher repetition frequencies (10 Hz) exhibited pits on its surface, unlike those grown at lower frequencies (2 Hz). XRD and resistivity measurements confirmed Ru-deficient stoichiometry in high-frequency-grown SrRuO₃, attributed to the formation of volatile RuO₄. HAADF-STEM analysis showed that the interface between Ba₀·₅Sr₀·₅TiO₃ and the SrRuO₃ bottom electrode was affected by the growth conditions. At higher repetition frequencies, Ru diffusion from the bottom electrode into the dielectric layer was observed, creating a gradient in the HAADF intensity. The capacitor with the SrRuO₃ bottom electrode grown at 2 Hz showed superior dielectric properties: a dielectric permittivity of 861 and a leakage current density of 5.15 × 10⁻⁶ A/cm² at 1 V, representing a four-order-of-magnitude reduction compared to the capacitor with the 10 Hz grown bottom electrode. UPS measurements indicated that the work function of SrRuO₃ remained constant regardless of growth frequency, ruling out material-induced conduction mechanisms. Temperature-dependent I-V measurements revealed hopping conduction in the 2 Hz sample and Poole-Frenkel emission in the 5 and 10 Hz samples. DFT calculations demonstrated that the combination of Ru substitution and oxygen vacancies created shallow in-gap states, acting as traps for Poole-Frenkel emission. The interface engineering strategy resulted in a significant reduction of these defects leading to the improved performance.

The substantial enhancement in the dielectric properties of the MIM capacitor is directly attributed to the successful interface engineering. The pit-free and stoichiometric SrRuO₃ bottom electrode grown at a low repetition frequency effectively suppressed defect formation at the interface. This led to a dramatic reduction in leakage current and improved dielectric permittivity, even with an ultra-thin dielectric layer. The DFT calculations provided crucial insight into the role of specific defects and their energy levels, supporting the experimental observations. The findings highlight the importance of controlling the electrode-dielectric interface for optimizing the performance of perovskite-oxide-based capacitors. The observed hopping conduction in the 2 Hz sample may suggest a different defect landscape compared to the Poole-Frenkel behavior at higher frequencies.

This study demonstrates a significant advancement in perovskite-oxide-based MIM capacitors through precise interface engineering. By controlling the growth parameters of the SrRuO₃ bottom electrode, defect formation was suppressed, leading to a remarkable reduction in leakage current and high dielectric permittivity, even with a 10 nm dielectric layer. This work paves the way for the development of high-performance perovskite-oxide-based capacitors for future DRAM applications. Future research could explore other interface engineering techniques, investigate different perovskite compositions, and further optimize the deposition process for even higher performance.

The study focused on a specific perovskite composition (Ba₀·₅Sr₀·₅TiO₃) and electrode material (SrRuO₃). The generalizability of these findings to other perovskite systems requires further investigation. While DFT calculations provided valuable insights, simplifying assumptions were made, and the accuracy of the model depends on the chosen parameters. Long-term reliability studies are needed to fully assess the performance of the interface-engineered capacitors under various operational conditions.