High-speed III-V nanowire photodetector monolithically integrated on Si

The paper addresses the challenge of monolithic integration of III-V optoelectronic devices on silicon to enable energy-efficient, high-bandwidth on-chip optical interconnects. Electrical interconnects in integrated circuits contribute significantly to power consumption, and integrated photonics promises better energy efficiency, higher bandwidth density, and lower cost per bit. State-of-the-art Ge photodetectors are mature but limited by indirect bandgap absorption and dark current, whereas III-Vs offer higher absorption and active emission but are difficult to integrate on Si due to lattice, polarity, and thermal mismatch. Nanowires reduce epitaxial mismatch constraints but prior approaches are typically vertical, pick-and-place, or otherwise not compatible with large-scale CMOS integration and high-speed operation. Only one prior monolithic NW detector on Si had ~3.1 GHz bandwidth, far below requirements. The research goal is to realize an in-plane, monolithically integrated III-V (InGaAs) p-i-n nanostructure photodetector on Si with ultra-low capacitance for high-speed, low-power operation, broad telecom spectral response, and potential co-integration with Si waveguides and III-V emitters.

The authors review progress and limitations in integrated photonics and detectors: Ge photodetectors in CMOS have achieved >70 GHz bandwidth and 100 GBd but often suffer from higher dark current and lower absorption due to the indirect bandgap. III-V materials (e.g., InGaAs) provide higher absorption and tunable direct bandgaps enabling lasers and LEDs, yet monolithic integration on Si is challenged by lattice/polarity/thermal mismatch. Nanowire strategies include growth on III-V substrates, Au-catalyzed growth on Si, and selective area growth on Si. However, most devices are vertical, rely on pick-and-place for lateral integration, or are not CMOS-compatible or scalable. Previous monolithically integrated NW detectors on Si have shown limited bandwidth (~3.1 GHz). Template-assisted selective epitaxy (TASE) has been used to integrate III-Vs on Si in-plane and to demonstrate electronic devices and optically pumped microdisks, suggesting a path for monolithic, in-plane optoelectronic devices.

Device concept and growth: In-plane InGaAs p-i-n nanostructures are integrated on silicon using template-assisted selective epitaxy (TASE) combined with in-situ doping. The top Si layer of an SOI wafer (2 µm BOX) is thinned to 60 nm (sets III-V height), patterned by e-beam lithography and ICP dry etch to define nanostructure templates and Si passives. An oxide template is formed by depositing 50 nm ALD SiOx and 150 nm PECVD SiO₂. Openings are etched in the SiOx to partially expose the patterned Si at one end. A TMAH wet etch partially removes the patterned Si to create a hollow oxide cavity with a remaining Si seed at one extremity, enabling epitaxial nucleation. Epitaxy: MOCVD growth at 550 °C fills the hollow oxide template. A ~20 nm InAs nucleation segment (TMIn, tertiarybutylarsine (TBA)) is grown at the Si interface for selective nucleation. Then InGaAs is grown (TMIn, TBA, triethylgallium (TBGa)) with V/III ratio 0.27. In-situ p- and n-doping are achieved by adding DEZn (p-type) and Si₂H₆ (n-type), respectively. The lateral p-i-n structure is formed by sequentially growing ~330 nm p-InGaAs, ~330 nm intrinsic InGaAs, and ~330 nm n-InGaAs starting from the Si seed. Final nanostructure dimensions: length ~1 µm, height 60 nm, width 60–500 nm (lithographically defined). Contacts are formed by Ni/Au lift-off. Structural characterization: Cross-sectional lamellas from five devices are prepared by FIB (FEI Helios Nanolab 450S) along the growth direction to reveal the Si/III-V interface. STEM imaging is performed on a JEOL JEM-ARM200F (200 kV, double aberration-corrected) for high-resolution and on a FEI Titan Themis (300 kV, ChemiSTEM) for EDS. EDS spectrum imaging uses 1.5 nA beam current, 0.8 nm pixel spacing, 4 µs dwell, with elemental maps from In Lα₁, Ga Kα₁/Kα₂ lines. Optical characterization (PL/EL): PL uses a ps-pulsed supercontinuum laser (NKT Extreme Red, 78 MHz), selecting 710, 720, 750 nm lines for excitation. Illumination and collection through a 10× objective; spectra recorded on a Princeton SP-2500i spectrometer with a cryogenically cooled InGaAs CCD (Princeton PyLoN-IR, cutoff ~1600 nm). Measurements at room temperature (low-T data in Supplementary). EL uses the same optical setup; electrical drive is a rectangular voltage at 10 kHz, 50% duty to avoid thermal damage; integration 10–50 s. Spectral response and DC characterization: Devices are illuminated from the top (10× objective) with a ps supercontinuum source; excitation wavelength swept 900–1800 nm. Electrical I–V and photocurrent are measured with a Keysight B1500A. Dark I–V characteristics are recorded without illumination. Responsivity and high-speed setup: A second setup uses a free-space-coupled fiber (NA 0.14) delivering a cw 1346 nm laser at ~10° incidence; fiber is positioned ~2 µm above the surface with optimized overlap to the p-i-n region. RF-compatible cross-like test structures are probed. S-parameters (S21) are measured with a vector network analyzer from 100 MHz to 30 GHz. Responsivity is computed from measured photocurrent and estimated incident power on the device area (details and bias dependence in Supplementary), using both intrinsic-region-only and whole-structure absorption assumptions. Simulations: 2D FDTD optical simulations (Sentaurus EMW) generate wavelength-dependent optical generation profiles with a monochromatic 6 dBm source placed 1 µm above the device at 10° incidence; metal contacts and SOI substrate included; 4 µm air above and lateral. The simulated p-i-n device height is 60 nm, total length 1.3 µm; uniform In composition of 55% is assumed. Electrical transport simulations (Sentaurus Device) use the optical generation as input, with SRH lifetime 1 ns for all carriers, electron mobility 1100 cm²/V·s, hole mobility 250 cm²/V·s, and experimentally measured doping concentrations. Spectral response from 1200–1700 nm is simulated with 50 nm steps. Device geometry and coupling: Current demonstrations use free-space coupling because the Si waveguide dimensions under the III-V are too small to support a guided mode; the in-plane architecture is designed for future butt-coupling to SOI waveguides.

• Monolithic in-plane InGaAs p-i-n nanostructure photodetectors were grown on Si using TASE with in-situ lateral doping. Device dimensions: height 60 nm, length ~1 µm, width 60–500 nm; footprint as low as ~0.06 µm²; estimated junction capacitance <0.1 fF.
• Material quality: Single-crystalline InGaAs epitaxially aligned to the Si seed; misfit dislocations confined at the Si/III-V interface; no threading dislocations observed; presence of stacking faults and short wurtzite segments in zincblende matrix. EDS shows In content x ≈ 47–53%, average ~50%; corresponding unstrained bulk ZB bandgaps ~0.78 eV (In₀.₄₇Ga₀.₅₃As) to ~0.74 eV (In₀.₅₃Ga₀.₄₇As).
• Electrical characteristics: Diode-like I–V with low dark currents. At -2 V: 60 nm wide device ~1.7 nA; 200 nm wide ~15 nA; 500 nm wide ~36 nA. Activation energy ~200 meV suggests a small barrier at the p-type contact.
• Spectral response: Photocurrent observed from ~1200 to 1700 nm with a maximum around ~1350 nm. 2D electro-optical simulations reproduce spectral features with two absorption peaks (~1350 nm and ~1650 nm) due to multi-reflections between Si substrate/BOX and metal contacts in free-space coupling.
• Responsivity and QE: At 1346 nm (cw), responsivity up to 0.68 A/W at -2 V with external quantum efficiency up to 62% (assuming generation primarily in the intrinsic region). Including carriers generated in doped regions, a conservative responsivity estimate is ~0.2 A/W.
• High-speed performance: Measured small-signal 3 dB bandwidth exceeds ~25 GHz (limited by 30 GHz measurement setup), the highest reported for nanostructure photodetectors to date. Clear 32 Gb/s NRZ eye diagram demonstrated at -2 V bias.
• Emission: PL shows emission around ~1600 nm; EL under forward bias exhibits a single emission peak in the C-band, consistent with PL and the InGaAs composition.
• Simulations and experiments are in good agreement regarding spectral dependence and absorption distribution under free-space illumination.

The demonstrated in-plane InGaAs p-i-n nanostructure photodetectors directly address the challenge of monolithic III-V integration on Si by leveraging TASE to form lateral junctions that are compatible with CMOS process flows and future waveguide coupling. Ultra-thin active regions and nanoscale footprints yield sub-femtofarad capacitances, enabling high-speed operation with low dark currents and competitive responsivity. The experimentally observed spectral response spanning O- and C-bands with peaks near 1350 and 1650 nm is consistent with device-scale optical interference under free-space coupling, as confirmed by TCAD simulations. The >25 GHz bandwidth and successful 32 Gb/s data reception show that nanostructure detectors can meet interconnect speed requirements. Dual-functionality as LEDs with C-band emission highlights the potential for co-integrated sources and detectors. In future waveguide-coupled implementations with improved optical confinement and tailored absorption lengths, responsivity and bandwidth-density are expected to improve further while preserving low capacitance and energy/bit advantages.

The work demonstrates the first ultrathin, monolithically integrated in-plane InGaAs p-i-n nanostructure photodetectors on Si with strong telecom-band performance. Key achievements include responsivity up to 0.68 A/W at 1346 nm, spectral response from 1200–1700 nm, low dark currents, and high-speed operation with a 3 dB bandwidth >25 GHz enabling 32 Gb/s data reception. Material analysis confirms high crystalline quality with minimal extended defects beyond the Si/III-V interface. TCAD simulations align with measured spectral behavior and indicate interference-driven absorption features under free-space coupling. The devices also exhibit C-band electroluminescence, indicating feasibility for integrated light sources. This lateral, CMOS-compatible TASE platform paves the way for dense III-V/Si co-integration of detectors and emitters butt-coupled to Si waveguides, enabling energy-efficient, high-bandwidth optical interconnects and broader applications in sensing and LiDAR. Future work should realize waveguide-coupled devices with optimized mode confinement, longer absorption regions, refined contact engineering, and full transceiver integration with Si CMOS.

• Current optical coupling uses free-space illumination; the underlying Si waveguides are too small to support guided modes, so waveguide-coupled performance is not yet demonstrated.
• Spectral response non-uniformity arises from interference effects and thin device geometry under free-space coupling; not representative of optimized waveguide-coupled devices.
• Responsivity estimation depends on incident power and illuminated area assumptions; alternative assumptions (including doped regions) reduce the value to ~0.2 A/W.
• Composition variations (In ~47–53%) along the structure correlate with dopant switching during MOCVD and may impact uniformity.
• Activation energy (~200 meV) indicates a small barrier at the p-type contact, potentially limiting forward conduction and injection.
• Measurement bandwidth is limited by the ~30 GHz instrumentation, so the true 3 dB bandwidth may exceed the reported >25 GHz.
• Simulations assume uniform In composition (55%) and cw-like average power for electrical transport, differing from pulsed experimental conditions.
• High PL pump powers are required to obtain sufficient emission; detector cutoff near ~1600 nm in the spectrometer affects EL/PL spectral capture.
• RF-compatible test structures (cross geometry) were used for measurement convenience, which may not be fully optimized for ultimate device performance.