Entanglement across separate silicon dies in a modular superconducting qubit device

The study addresses how to realize scalable, modular quantum processors by directly coupling separate superconducting-qubit modules while maintaining high-fidelity entangling operations. Prior approaches to modularity include probabilistic, heralded entanglement over networks and deterministic microwave links between cryogenic systems, but for superconducting processors these methods are unlikely to surpass local two-qubit gates in speed and fidelity. The authors hypothesize that closely spaced, directly coupled dies can deliver inter-module gates with performance approaching intra-chip couplers, while offering benefits such as reduced cross-talk, mitigation of correlated errors (e.g., from radiation), and improved yield via smaller, replaceable modules. The purpose is to demonstrate deterministic inter-die coupling enabling parametric two-qubit gates and to validate entanglement quality, including simultaneous Bell violations across multiple inter-die links, thereby establishing a foundation for modular superconducting quantum computing.

The paper situates modular quantum computing across scales from nanometers to kilometers. It notes heralded entanglement protocols achieving up to ~200 Hz rates and advances in deterministic microwave links enabling state transfer and remote entanglement between spatially separated superconducting systems. However, for integrated superconducting processors, local two-qubit gates reach tens of MHz coupling and ~99.9% fidelity, setting a high bar. Modular, multi-die architectures may reduce cross-talk and correlated errors (e.g., due to cosmic/background radiation) and improve yield via smaller, repeatable units. Prior work on 3D integration and multilayer microwave circuits informs this approach. The authors build on parametric entangling gates for transmons and previous chip-to-chip demonstrations, aiming to show robust, deterministic inter-die coupling without sacrificing gate or coherence performance.

Device and architecture: Four nominally identical eight-qubit integrated circuits (QulCs) fabricated on separate silicon dies are flip-chip bonded onto a larger carrier chip. Each QulC hosts four flux-tunable and four fixed transmon qubits with associated readout resonators and flux control lines. Inter-die coupling is capacitive via paddle-shaped couplers on the QulC aligned over matching couplers on the carrier; there is no intentional intra-die qubit coupling on this test platform to isolate inter-chip behavior. Qubits are read out in a multiplexed fashion (four per line), and the assembled device is measured at ~10 mK in a dilution refrigerator.

Fabrication and bonding: QulCs use standard lithography with Al/AlOx/Al Josephson junctions via double-angle evaporation and Nb ground planes and coplanar structures. The carrier chip features Si cavities (24 µm deep) coated with a Nb/MoRe superconducting shield and indium bumps deposited on the top surface. Indium bumps (~6.5 µm thick, 40 µm diameter pre-bond) are patterned by lift-off and deposited by e-beam evaporation. Flip-chip thermo-compression bonding aligns each QulC to the carrier (±2.5 µm lateral, ±0.5 µm parallelism), bonding sequentially at 70 °C for the QulC (carrier at 30 °C) and cooling with N2. Post-bond bump heights set inter-die spacing; variation (1.5–4 µm) affects coupling.

Hamiltonian design and parametric gates: Circuit parameters are extracted via quasi-static EM simulation and a positive second-order representation for the linearized circuit; transmon nonlinearity is included perturbatively. Designed coupling between inter-die pairs targets ~12 MHz for a 3 µm bump height. Due to process variation, room-temperature junction conductance is used to refine Josephson energies and predict device frequencies. Parametric gates are implemented by AC flux-modulating the tunable qubit around its parking point, generating sidebands at f_T,01 + k f_p. Aligning a sideband with the partner’s transition frequency activates coherent exchange at a rate given by the bare coupling scaled by sideband weight. iSWAP uses f_p = (f_T,01 − f_F,01)/2 with a π rotation; CZ uses coupling between |11⟩ and |02⟩ or |20⟩ at f_p = (f_T + f_F)/2 or (f_T − f_F)/2 with a 2π rotation.

Coupling characterization: Bare coupling g is inferred from the qubit-qubit dispersive shift χ_qq measured via a modified time Ramsey sequence. For each coupled pair, χ_qq is measured in both directions by preparing one qubit in |0⟩ and |1⟩ while Ramsey-probing the other, and g is extracted using perturbative transmon–transmon dispersive theory. Post-experiment, destructive shear exposes bonded indium bumps; post-bond diameters, combined with known pre-bond dimensions, estimate bump heights to correlate with simulated g.

Gate calibration and benchmarking: Two-qubit parametric gates (CZ for all pairs; iSWAP for some) are calibrated and benchmarked using two-qubit randomized benchmarking (RB) and interleaved RB (iRB). iRB is reported when FRB ≥ 92% to bound iRB bias. Coherence-limited fidelities are computed from T1 and T2 measured under modulation of the tunable qubit at the gate frequency (T1_mod, T2_mod), emulating gate conditions. Stability over ~24 h is assessed by repeated re-tuning, readout calibration, coherence measurement, and iRB benchmarking.

Bell test across disjoint inter-die links: Three disjoint inter-chip connections (A0–B7, B0–C7, C1–D6) are prepared in Bell states |Ψ⟩ = (|00⟩ + |11⟩)/√2 using CNOTs compiled from CZs and single-qubit gates. Measurements are performed in ZZ and XX bases (with/without final Hadamards). For each of 100 runs, 10 shots per basis are collected simultaneously on all pairs. The CHSH-type witness W_k = QS + RS + RT − QT is computed per pair, with total W = Σ_k W_k, and compared to classical (2N) and quantum (2N√2) bounds for N = 3 disjoint pairs.

• Inter-die capacitive coupling achieved and characterized: measured bare coupling g across pairs ranged from 13.26 ± 0.59 MHz to 18.94 ± 0.39 MHz, consistent with variation from post-bond indium bump heights (1.55–2.18 µm measured, with simulations predicting 16.86–24.52 MHz for those heights). Measured g was ~20% lower than simulations on average.
• High-fidelity inter-die entangling gates: CZ gates calibrated on 10/12 pairs showed measured fidelities mostly limited by qubit coherence under modulation. Five of twelve CZs exceeded 95% fidelity; best CZ fidelity reported 98.34 ± 0.31% (A0–B7). The best inter-die iSWAP gate reached 99.1 ± 0.5% (iRB) on C1–D6, with RB fidelity 95.8 ± 0.2%.
• Coherence impact: Qubit T1 and T2 distributions for inter-chip-coupled qubits were statistically similar to baseline devices without inter-chip couplers, indicating the coupler did not degrade relaxation or dephasing. Gate fidelities tracked T1 fluctuations; fidelity dipped when T1 < ~10 µs but was typically centered around ~98% for the best pair over 24 h.
• Simulated error analysis: Across expected bump heights, predicted coherence-limited and unitary (coherent) errors suggested maximum achievable fidelities in the ~99.0–99.5% range, relatively insensitive to h within the observed spread.
• Simultaneous Bell inequality violation across four dies: For three disjoint inter-die pairs, individual witnesses were W_AB = 2.184 ± 0.060, W_BC = 2.183 ± 0.034, W_CD = 2.284 ± 0.029, each exceeding the classical bound of 2 by >3σ. The total figure of merit was W_total = 6.651 ± 0.067, surpassing the classical bound 2N = 6 by ~10σ (N = 3), confirming concurrent entanglement across all four chips.

The results demonstrate that deterministic, capacitive inter-die coupling via flip-chip bonded paddles can deliver inter-module entangling operations with fidelities approaching intra-chip state-of-the-art while not degrading qubit coherence. The gate performance is chiefly limited by T1/T2 under modulation, similar to monolithic devices, indicating the inter-chip coupling mechanism itself is not a dominant error source. The ability to simultaneously violate Bell inequalities on three disjoint pairs spanning four dies establishes that multiple inter-die links can operate concurrently without prohibitive cross-talk or correlated errors. This modular approach provides practical advantages—improved yield via identical QulCs, potential reduction of correlated errors through physical separation, and flexible assembly—pointing toward scalable, fault-tolerant architectures. The observed variability in coupling due to bump height spread did not strongly affect achievable fidelities within the tested range, but tightening fabrication tolerances or redesigning coupler geometry could further optimize performance and support advanced tunable-coupler schemes. The architecture invites exploration of system-level benefits, such as isolation from radiation-induced correlated events and phonon propagation suppression across die boundaries, which are pertinent for robust error-corrected quantum computing.

This work establishes a modular superconducting qubit platform comprising four flip-chip-bonded, interchangeable silicon dies with deterministic inter-die capacitive coupling. It achieves high-quality two-qubit gates across dies, including a 99.1 ± 0.5% iSWAP and CZ fidelities up to 98.3 ± 0.3%, and demonstrates simultaneous Bell inequality violations across three disjoint inter-die pairs involving all four chips. Gate errors are primarily coherence-limited, and inter-chip couplers do not measurably degrade qubit T1/T2 relative to baseline devices. These results validate the fundamental building blocks for modular solid-state quantum processors and chart a path toward scalable, fault-tolerant architectures. Future directions include: reducing coupling variability (e.g., improved bonding force control and paddle geometry), integrating tunable coupler schemes, adding intra-chip connectivity to form larger lattices, developing pre-bond or reconfigurable interconnect testing to enhance yield, and systematically studying mitigation of correlated errors (radiation, phonons) leveraging die isolation.

• Fabrication variability in indium bump heights led to a spread in coupling strengths; measured g values were ~20% lower than simulated predictions, indicating modeling and/or metrology inaccuracies (e.g., bump height estimation, material properties, next-nearest neighbor effects).
• Two of twelve inter-die pairs could not be fully benchmarked due to fabrication frequency targeting errors placing modulation frequencies outside the control electronics band and degraded AC flux control.
• Some gates exhibited increased dephasing under modulation due to two-level systems (TLS), limiting CZ fidelities on certain pairs.
• Gate fidelity stability depended on T1 fluctuations; fidelity degraded when T1 dropped below ~10 µs, reflecting environmental/temporal variability not yet mitigated.
• The use of permanent indium bonds prevents replacement of individual QulCs post-bonding, limiting post-fabrication reconfiguration; future reconfigurable interconnects or pre-bond cryogenic testing could alleviate this.