All-2D CVD-grown semiconductor field-effect transistors with van der Waals graphene contacts

The increasing demand for sustainable and energy-efficient electronics fuels the search for innovative materials and device architectures. Two-dimensional (2D) materials, particularly transition metal dichalcogenides (TMDs) like molybdenum disulfide (MoS2), and van der Waals (vdW) heterostructures offer a compelling pathway towards this goal. Their unique properties, including high carrier mobility, tunable bandgaps, and atomically thin nature, make them ideal candidates for next-generation transistors, rectifiers, light-emitting diodes, and solar cells. However, realizing the full potential of these materials requires overcoming several challenges, including the formation of low-resistance contacts, the development of suitable gate dielectrics and electrodes, and the enhancement of channel mobility. Graphene, with its exceptional electrical conductivity and tunable Fermi level, emerges as a promising contact material for 2D semiconductors. The vdW nature of the interface between graphene and TMDs allows for the creation of heterostructures without the constraints of lattice matching, thus enhancing the versatility of device design. While exfoliated materials have been used for preliminary investigations, large-area 2D materials grown via chemical vapor deposition (CVD) are essential for scalable industrial applications. This study focuses on the detailed electronic transport and correlation properties of all-CVD-grown MoS2 FETs with graphene contacts to understand mobility limitations and metal-insulator transition (MIT) properties, a critical step towards the development of high-performance, scalable 2D devices.

Extensive research has explored the potential of 2D materials for advanced electronics. Studies have demonstrated the feasibility of 2D transistors with exceptional performance metrics, including high on-off ratios and carrier mobilities. However, challenges remain in achieving low-resistance contacts to 2D semiconductors and improving the overall device stability and reproducibility. Graphene has shown promise as a contact material, mitigating Fermi-level pinning and enabling gate-tunable Schottky barriers. The combination of graphene and 2D semiconductors has shown potential in sub-nm gate length transistors, mitigating Fermi-level pinning in electronics and solar cells, and enhancing photodetection sensitivity. While previous research has focused on exfoliated materials, the limitations of scalability necessitates the exploration of CVD-grown 2D materials for practical applications. This research addresses the gap in knowledge regarding the electronic transport properties and correlation effects in all-CVD-grown 2D semiconductor FETs with graphene contacts. This knowledge is critical for understanding and overcoming the existing limitations to building high-performance and scalable 2D-based electronic devices. Existing literature on CVD-grown 2D materials has addressed aspects of material growth and device fabrication, however, the complete analysis of transport properties, particularly the temperature dependence and the gate and bias-induced MIT, remains lacking.

The fabrication process involved transferring CVD-grown graphene (from Graphenea) onto a SiO2/Si substrate, patterning it into stripes via electron-beam lithography (EBL) and O2 plasma etching. CVD-grown monolayer MoS2 was then transferred onto the graphene stripes using a wet transfer technique. Metallic contacts (1 nm TiO2/80 nm Co) were deposited using EBL and e-beam evaporation, followed by lift-off. Raman spectroscopy confirmed the quality of the graphene and MoS2 layers. Four-terminal measurements were used to characterize the electrical properties of the individual materials and the complete heterostructure device. Temperature-dependent transport measurements were conducted in a vacuum cryostat using a Keithley 2612B dual-channel source meter. The Schottky barrier height was estimated using the thermionic emission model, and the mobility was extracted from the transfer characteristics. The variable-range hopping (VRH) model was used to explain the observed metal-insulator transition behavior. The channel width was approximated by averaging the channel width at the source and drain electrodes and the distance between the two electrodes was considered as channel length. No annealing was performed during fabrication, but the authors acknowledge that proper annealing and encapsulation could enhance the device performance further. The highly doped SiO2/Si substrate served as a back gate for controlling the carrier concentration in both the graphene and MoS2 layers. The detailed characterization included Raman spectroscopy for material quality assessment, four-point probe measurements for graphene resistivity, and FET characterization involving I-V curves and transfer characteristics at various temperatures and bias voltages. The temperature-dependent data were fitted with power-law equations for mobility and variable-range hopping models for conductivity to determine the mechanisms governing transport properties at different temperatures and bias conditions.

The fabricated all-2D CVD MoS2 FETs with graphene contacts demonstrated low and tunable Schottky barriers, high ON currents, and good channel mobility. The graphene contacts effectively mitigated Fermi-level pinning, leading to improved device performance compared to devices with conventional metallic contacts. Temperature-dependent transport measurements revealed dominant phonon scattering at higher temperatures (T ≥ 230 K) and impurity scattering at lower temperatures (T ≤ 230 K). A gate- and bias-induced metal-insulator transition (MIT) was observed, characterized by a change in conductivity with temperature, from insulating behavior at lower biases to metallic behavior at higher biases. Analysis using the variable-range hopping (VRH) model indicated that the MIT is due to the hopping of carriers through localized states, with the localization length increasing with increasing gate voltage and bias. Specifically, the flat-band Schottky barrier was 52 meV at around Vg = 13 V. The Schottky barrier decreased with increasing Vg. At Vg ≥ 30 V, the calculation deviated from the thermionic emission model, preventing further estimation of SB. At lower temperatures and lower Vds, insulating behavior was seen. However, at higher Vds (>60 V) and high temperature range (200-300 K), metallic properties were observed. The localization length (ξ) increased linearly with gate voltage (Vg) at Vds = 1 V, reaching 25 nm, and further increased to 50 nm at higher Vds, coinciding with the emergence of partial MIT. The estimated mobility (µ) showed a slight increase with temperature at lower T due to impurity scattering (µ ∝ T0.1), and a drastic decrease at higher T due to phonon scattering (µ ∝ T−1). The on-off ratio was approximately 106 and subthreshold swing (SS) was 5.88 V/dec in the all-2D FET.

The findings demonstrate the potential of using all-CVD-grown 2D materials for high-performance FETs. The tunable Schottky barrier at the graphene-MoS2 interface offers advantages for device optimization. The observed phonon and impurity scattering mechanisms are consistent with other studies on 2D materials, highlighting the importance of material quality and defect control. The gate- and bias-induced MIT, explained by the VRH model, indicates the crucial role of localized states in the transport properties of these devices. This research directly addresses the challenges related to contact resistance and mobility limitations in 2D FETs. The successful integration of graphene contacts significantly improves device performance. The observed MIT, although partially explained by the VRH model, warrants further investigation to fully understand the underlying mechanisms. These results provide valuable insights into the charge transport properties of all-CVD-grown MoS2-graphene heterostructures, offering guidance for future device optimization and the design of novel electronic and optoelectronic applications.

This work successfully demonstrated high-performance all-2D CVD-grown MoS2 FETs with graphene contacts, showcasing improved mobility and tunable Schottky barriers. The study elucidated the dominant scattering mechanisms and revealed a gate- and bias-induced metal-insulator transition. These findings offer critical insights into the transport properties of 2D semiconductor heterostructures and pave the way for developing advanced, scalable, and energy-efficient electronic devices. Future research could focus on exploring different CVD growth methods to further enhance material quality and minimize defects, optimizing the graphene contact fabrication process to reduce contact resistance, and investigating more advanced device architectures such as vertical heterostructures to improve device performance.

The study focused on a limited number of devices, and the results may not be fully generalizable. The channel width approximation in the mobility calculations could introduce some uncertainty. The VRH model, while offering a good explanation for the MIT, does not fully capture the complexity of the transport mechanisms. Further research is needed to investigate the exact origin of the bias-induced MIT, exploring factors such as quantum phase transitions and percolation effects. The absence of annealing and encapsulation may affect the ultimate transport characteristics, and further optimization in these aspects could improve the device performances.