All-2D CVD-grown semiconductor field-effect transistors with van der Waals graphene contacts

The study addresses the challenge of realizing scalable, energy-efficient electronics based on 2D semiconductors, where device performance is limited by issues such as high contact resistance, appropriate gate dielectrics/electrodes, channel mobility, wafer-scale growth, encapsulation, and reliable doping. Graphene-based vdW heterostructures with 2D semiconductors offer sub-nm gate lengths, gate-tunable Schottky barriers, mitigation of Fermi-level pinning, and enhanced optoelectronic functionalities. Prior work has largely relied on exfoliated materials, which are unsuitable for industrial-scale implementation. There is a need to explore all-2D CVD-grown devices to enable batch fabrication and integrated circuits. The research question focuses on how vdW graphene contacts to CVD-grown MoS2 affect electronic transport, including contact Schottky barriers, mobility-limiting scattering mechanisms, and the presence and nature of gate- and bias-induced metal-insulator transitions across temperature.

The paper situates its contribution within efforts to leverage 2D materials for advanced electronics, photonics, and energy devices, highlighting progress in graphene integration, sub-1-nm gate length MoS2 transistors, and vdW heterostructures enabling tunable Schottky barriers and reduced Fermi-level pinning. Prior studies primarily employed exfoliated flakes for proof-of-concept devices, while scalable CVD growth is essential for industrial relevance. Reports of graphene/MoS2 heterointerfaces show improved contacts and gate-tunable barriers, and variable-range hopping (VRH) as a transport mechanism in 2D semiconductors has been linked to gate/bias-induced metal-insulator transitions. However, comprehensive transport and correlation studies in all-CVD MoS2 FETs with graphene contacts, especially mapping mobility-limiting factors and MIT behavior across temperature and bias, have remained scarce.

- Materials and device fabrication: CVD monolayer graphene (grown on Cu, wafer-scale) was transferred onto highly doped Si/SiO2 substrates (285–300 nm SiO2). Graphene was patterned into stripes by electron-beam lithography (EBL) and O2 plasma etching, followed by solvent cleaning. Monolayer, triangular CVD MoS2 (typical size 50–100 µm) grown per George et al. was wet-transferred onto the patterned graphene to form MoS2/graphene vdW heterostructures. - Contacts and device geometry: For characterization, metallic tunnel contacts (1 nm TiO2/80 nm Co via e-beam evaporation) were used on MoS2 in specific tests to probe material properties, while the all-2D FETs used graphene as source/drain contacts. Lift-off was performed in warm acetone (65 °C). The highly doped Si substrate acted as a global back gate. Typical all-2D device channel length and width were approximately 11 µm and 10.75 µm (non-uniform MoS2 shapes handled by averaging widths at source/drain and using electrode spacing as length). - Structural and material characterization: Raman spectroscopy (638 nm laser) was used to assess graphene (high 2D/G ratio, minimal D-peak indicating monolayer with low defects) and monolayer MoS2 (characteristic E2g and A1g modes). - Electrical measurements: Graphene channels were characterized via four-terminal measurements to extract Dirac point and field-effect mobility. MoS2 FETs (with both metal and graphene contacts) were measured at room temperature and across temperatures (70–300 K) under vacuum in a cryostat using a Keithley 2612B. Transfer (Ids–Vg) and output (Ids–Vds) characteristics were recorded for various Vds. Gate capacitance per area Cg = 1.15 × 10−8 F cm−2 was used for mobility extraction. - Schottky barrier extraction: Temperature-dependent Ids–Vg at fixed Vds were analyzed using a thermionic emission model; Arrhenius plots of ln(Ids/Tn) versus 1000/T (n ~ 1.5–2 as used in analysis) at different Vg determined the Schottky barrier height and flat-band barrier. - Mobility versus temperature: Mobility µ(T) was extracted and fit to a power-law µ ∝ T^γ to distinguish impurity (weak T dependence) versus phonon (negative T exponent) scattering regimes. - Metal-insulator transition and VRH analysis: Temperature- and bias-dependent conductance was analyzed within a 2D variable-range hopping framework. Arrhenius-like plots of ln(σT) versus T−1/3 provided the characteristic hopping parameter T0 and localization length ξ ∝ 1/T0^{1/3} as a function of gate voltage and drain bias (Vds = 1, 5, 10 V).

- Graphene channel properties: Dirac points at Vg ≈ 8 V (under MoS2) and 15 V (pristine graphene). Maximum field-effect mobility µe ≈ 1260 cm^2 V−1 s−1 (heterostructure region) and 900 cm^2 V−1 s−1 (pristine), attributed to protection from residues by the overlying MoS2. - MoS2 FET with conventional metal contacts (room temperature): n-type behavior; Ids increases with positive Vg. Extracted mobility µ ≈ 1.9 cm^2 V−1 s−1, on/off ratio ≈ 10^6, threshold voltage Vth ≈ 5.5 V, subthreshold swing SS ≈ 1.42 V/dec. - All-2D MoS2 FET with graphene contacts (room temperature): Higher Ids and µ, and lower Vth compared to metal-contacted devices. Extracted values: Vth ≈ −35 V, on/off ≈ 10^6, SS ≈ 5.88 V/dec, mobility µ ≈ 14.5 cm^2 V−1 s−1. Slight nonlinearity in I–V at higher Vg attributed to long channel (~11 µm) and vdW contact gap. - Gate-tunable Schottky barrier: Using thermionic emission analysis at Vds = 1 V, the flat-band Schottky barrier height ΦFB ≈ 52 meV around Vg ≈ 13 V. SB decreases with increasing Vg; for Vg ≥ 30 V, data deviate from pure thermionic emission behavior, limiting extraction. - Mobility-limiting mechanisms versus temperature: µ(T) follows power laws with distinct regimes: for T ≤ 230 K, weak T dependence (γ ≈ 0.1) indicating impurity scattering dominance; for T ≥ 230 K, strong decrease with T (γ ≈ −1) consistent with phonon-limited transport. - Gate- and bias-induced partial MIT: At Vds = 1 V, devices show insulating behavior across 70–300 K (Ids increases with T). At higher Vds (5–10 V) and high gate bias (Vg ≳ 60 V) in the 200–300 K range, metallic-like behavior appears (Ids decreases with T), while at lower Vg or lower T (70–200 K) transport remains insulating, indicating a partial MIT controlled by gate and drain bias. - VRH interpretation and localization length: 2D VRH analysis indicates that the localization length ξ increases with gate bias; at Vds = 1 V, ξ increases linearly with Vg up to ~25 nm; at Vds = 5–10 V, ξ reaches up to ~50 nm, correlating with the emergence of partial MIT due to enhanced screening of trap states at higher carrier densities and biases.

Using all-CVD-grown MoS2 channels with vdW graphene contacts, the study demonstrates that tuning the graphene Fermi level via back gate simultaneously modulates the band alignment at the MoS2/graphene interface, minimizing the Schottky barrier and mitigating Fermi-level pinning. This yields improved channel transport metrics compared to conventional metal contacts, including higher mobility and lower threshold voltage. Temperature-dependent analyses reveal that impurity scattering limits mobility at low temperatures, while phonon scattering dominates at higher temperatures. The observed transition from insulating to metallic-like behavior with increased gate and drain biases at elevated temperatures is consistent with a 2D variable-range hopping mechanism in which increased carrier density and electric field screen trap potentials, increasing localization length and enabling percolative transport. These findings clarify how contact engineering with graphene and electrostatic control impact contact barriers, carrier scattering, and the onset of metal-insulator transitions in scalable, all-CVD 2D FETs, guiding optimization strategies for device performance across operating temperatures.

The work demonstrates scalable, all-2D CVD-grown MoS2 FETs with vdW graphene contacts that provide gate-tunable band alignment, reduced Schottky barriers (flat-band ΦSB ≈ 52 meV), and enhanced field-effect mobility relative to metal-contacted devices. Comprehensive temperature-dependent transport establishes impurity and phonon scattering as key mobility-limiting mechanisms and reveals gate- and bias-driven partial MIT consistent with 2D VRH transport and trap-state screening. These insights underscore the advantages of graphene contacts in overcoming Fermi-level pinning and improving transport in wafer-scale 2D devices. Future directions include refining contact and channel engineering (e.g., optimized annealing, passivation, encapsulation), exploring dielectric and substrate effects, systematic scaling of channel geometry, and theoretical/experimental studies to conclusively determine the mechanisms underlying MIT and its scaling behavior in 2D semiconductors.

- Transfer characteristics in the graphene-contacted MoS2 FET did not reach off-saturation at low Vg, potentially affecting on/off ratio and subthreshold swing estimation. - Thermionic emission model deviates at higher gate biases (Vg ≥ 30 V), limiting accurate Schottky barrier extraction in that regime. - Long channel length (~11 µm) and vdW gaps can introduce nonlinearity in I–V characteristics. - Devices were not annealed; improved annealing, passivation, and encapsulation could further enhance transport and reduce extrinsic scattering. - Exact origins of gate- and bias-induced MIT remain unresolved; possible confounding factors include weak localization, trap states, self-heating, and intermediate carrier densities. - Non-uniform MoS2 channel geometry necessitated approximations in width/length for mobility extraction.