Ferroelectric field-effect transistors (FE-FETs) hold significant promise for next-generation low-power electronics due to their non-destructive readout capability and inherent energy efficiency. However, integrating high-performance ferroelectric materials onto silicon platforms remains a major challenge. Hafnia-based ferroelectrics, particularly Hf₀.₅Zr₀.₅O₂ (HZO), have shown great potential owing to their CMOS compatibility. Nevertheless, achieving robust ferroelectricity in thicker films (beyond the typically optimal ≤10 nm) while maintaining device-to-device uniformity is crucial for large-scale integration (LSI). This necessitates the exploration of alternative CMOS-compatible ferroelectric materials with superior scalability. This study focuses on the development and characterization of ZrₓAl₁₋ₓOᵧ (ZAO), a potentially cost-effective and abundant alternative to HZO, as a ferroelectric gate dielectric for high-performance TFTs. The research investigates the possibility of inducing ferroelectricity in ZAO through the application of compressive strain during the growth of a ZnO layer. The overall goal is to demonstrate the feasibility of using FE-ZAO TFTs for energy-efficient multi-level memory and neuromorphic computing applications. The successful integration of ZAO into TFTs with high performance metrics would contribute significantly to the advancement of low-power electronics.

Previous research has explored various dopants in HfO₂ and ZrO₂ to enhance ferroelectric properties. The metastable orthorhombic and rhombohedral phases have been identified as crucial for bistable polarization. Studies have shown that compressive strain can stabilize the ferroelectric rhombohedral (R3m) phase in pure ZrO₂ and HZO, even in thicker films (≥20 nm). Epitaxial growth on suitable substrates has proven effective in achieving this. However, the challenge remains to achieve this in a CMOS-compatible and scalable manner. The research on FE-FETs for multi-level memory and neuromorphic computing is also extensive, highlighting the need for large memory windows, high Ion/Ioff ratios, and low off-state currents. The gate stack engineering, particularly band offsets, plays a crucial role in minimizing gate leakage current (IG) for reliable device performance. This prior work serves as the foundation for this research, aiming to address the limitations of existing ferroelectric materials and device architectures.

The fabrication of inverted staggered ZAO-gated ZnO TFTs involved several steps: (1) Deposition of a Mo/IZO gate electrode by sputtering; (2) Spray pyrolysis deposition of ZAO films (40, 50, and 60 nm) at 360 °C; (3) Spray pyrolysis growth of ZnO films (30, 40, and 50 nm) at 350 °C on the ZAO; (4) Patterning of ZnO and ZAO layers to form the active island and contact holes; and (5) Deposition and patterning of Mo source and drain electrodes. The thickness of the ZAO and ZnO films was controlled by varying the number of spray cycles. Metal-ferroelectric-semiconductor-metal (MFSM) capacitors were also fabricated for investigating the ferroelectric properties of ZAO. Electrical characterization included I-V measurements using a semiconductor parameter analyzer, capacitance-voltage (C-V) measurements using an LCR meter, and polarization-voltage (P-V) measurements using a ferroelectric tester. Microstructural analysis employed grazing incidence X-ray diffraction (GI-XRD), high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM), and energy-dispersive spectroscopy (EDS). The multi-level memory and neuromorphic computing characteristics were assessed by applying various voltage pulses to the gate terminal and measuring the drain current. A multilayer perceptron (MLP) neural network simulator was used to evaluate the synaptic performance in a pattern recognition task using the MNIST database.

The 40 nm thick ZAO MFSM capacitor exhibited a remnant polarization (2Pr) of 15.2 µC cm⁻² at 10 kHz and a coercive electric field (Ec) of around 1.1 MV cm⁻¹. The capacitance-voltage (C-V) curves showed a clear bowknot-like anti-clockwise hysteresis. The FE-ZAO gated ZnO TFT demonstrated excellent performance: a memory window (MW) of 3.84 V, a subthreshold swing (SS) of 55 mV dec⁻¹, a high Ion/Ioff ratio of ≈10⁷, and a low off-state current of 1 pA. GI-XRD and HAADF-STEM analyses confirmed the presence of the ferroelectric rhombohedral R3m phase in the nanocrystalline ZAO. The d-spacings (d₁₁₁ = 3.037 Å and d₁₁₋₁ = 2.927 Å) and the angle (≈71.7°) between the [111] and [11-1] directions were consistent with the R3m phase. Multi-level memory operation was demonstrated with distinct current levels corresponding to different programming pulses. In neuromorphic computing simulations, the FE-ZAO TFT exhibited a high learning accuracy of 91.82% in a digit image classification task using an MLP neural network, demonstrating its potential as an artificial synapse. The high performance is attributed to the low nonlinearity values of LTP and LTD (-0.25 and 0.33 respectively) and a large on/off ratio of 21.67. The compressive strain induced by the ZnO growth at 350 °C plays a critical role in stabilizing the ferroelectric R3m phase in ZAO. This process resulted in uniform and reliable FE-TFT characteristics.

The findings demonstrate the successful realization of high-performance FE-ZAO gated ZnO TFTs for multi-level memory and neuromorphic computing. The use of compressive strain during ZnO growth effectively induces the ferroelectric R3m phase in ZAO, even in relatively thick films (40 nm). The device performance metrics achieved are comparable to, or even surpass, those of many state-of-the-art FE-FETs. The successful demonstration of multi-level memory and the high learning accuracy in neuromorphic computing simulations showcase the potential of FE-ZAO TFTs for next-generation energy-efficient electronics. The abundance and lower cost of Zr and Al compared to Hf further enhance the appeal of this approach. The results suggest that FE-ZAO could be a promising candidate for replacing HZO in future low-power electronics.

This research successfully demonstrated ferroelectric ZrxAl₁₋ₓOᵧ (ZAO) as a viable gate dielectric for high-performance thin-film transistors (TFTs). The compressive strain induced during ZnO growth enabled the stabilization of the ferroelectric R3m phase in ZAO, leading to excellent device performance in multi-level memory and neuromorphic computing applications. The results highlight the potential of FE-ZAO TFTs as a cost-effective and energy-efficient solution for next-generation electronics. Future studies could explore different ZAO compositions, optimization of the ZnO growth process, and integration with different semiconductor materials to further improve device performance and scalability.

While the study demonstrates promising results, there are some limitations to consider. The study primarily focused on a specific ZAO composition and ZnO growth conditions. Further investigation into other compositions and process parameters might lead to further performance improvements. The long-term stability and reliability of the devices under various operating conditions still require more comprehensive testing. The neuromorphic computing simulations were based on a specific neural network architecture and dataset. The generalizability of the results to other network architectures and tasks warrants further investigation. Finally, the scalability and manufacturability of the fabrication process for large-scale integration need to be addressed in future research.