Transistors with ferroelectric ZrxAl₁₋ₓOY crystallized by ZnO growth for multi-level memory and neuromorphic computing

The study addresses the challenge of realizing ferroelectric field-effect transistors (FE-FETs) that are compatible with large-scale, low-power electronics beyond ultra-thin hafnia-based films and silicon platforms. Although hafnia-based ferroelectrics (e.g., Hf0.5Zr0.5O2) show robust polarization in ultra-thin films, thicker films typically suffer from nonpolar phases, limiting scalability and uniformity. The authors hypothesize that ferroelectricity can be induced in Zr–Al oxide (ZrxAl1−xOy, ZAO), a CMOS-abundant material system, by exploiting compressive strain from a ZnO overlayer to stabilize a polar rhombohedral (R3m) phase, even at thicknesses ≥20–40 nm. The purpose is to demonstrate strain-induced ferroelectricity in ZAO, integrate it in ZnO thin-film transistors, and evaluate performance for multi-level memory and neuromorphic computing, where large memory window, low leakage, steep subthreshold swing, and programmable intermediate polarization states are crucial.

Prior work established ferroelectricity in hafnia-based oxides with orthorhombic phases (Pca21, Pmn21) responsible for switchable polarization, predominantly in ultra-thin films and often requiring high-temperature processing. Rhombohedral R3m ferroelectric phases have been reported in epitaxially strained ZrO2 and HZO, including thicker films via epitaxy or compressive strain. Studies show thickness-dependent phase stability, wake-up-free behavior in R3m, and stress/strain as key drivers of phase stabilization in fluorite-derived ferroelectrics. Band offset considerations highlight Al2O3’s higher CB/VB offsets on Si compared to HfO2/ZrO2 for leakage suppression. The need for thicker, CMOS-compatible ferroelectrics with reliable device-to-device uniformity for LSI motivates exploring abundant oxides (ZrO2, Al2O3) and strain engineering. This work extends these insights by demonstrating R3m ferroelectricity in thicker ZAO induced by ZnO growth via spray pyrolysis and assessing device-level memory and neuromorphic functions.

- Materials and deposition: - ZAO precursor: 0.15 M using 1:1 molar ratio Zr(acac)4 and Al(acac)3 in DMF:MeOH (7:3), stirred 6 h at 70 °C under N2; filtered (0.45 µm PTFE). - ZnO precursor: 0.2 M zinc acetate dihydrate in 2-methoxyethanol, stirred 6 h at room temperature under N2; filtered. - ZAO deposition: spray pyrolysis at 360 °C; solution flow 1 ml/min; nozzle speed 7 cm/s; nozzle–substrate distance 11.5 cm; repeated cycles with intermediate curing (3 min at 360 °C) and one-scan Ar/O2 plasma (12/20 sccm, 230 W) to reach ~40, 50, 60 nm; final anneal 1 h at 360 °C in air. - ZnO deposition: spray pyrolysis at 350 °C; 2 ml/min; nozzle speed 7 cm/s; distance 11.5 cm; 6/8/10 cycles for ~30/40/50 nm. - Device fabrication: - Substrate: glass. - Gate: 50 nm Mo + 15 nm IZO sputtered and patterned (IZO to prevent Mo oxidation during ZAO deposition). - Gate insulator: ZAO (40/50/60 nm) by spray pyrolysis and annealed. - Semiconductor: ZnO (30/40/50 nm) spray-deposited; ZAO/ZnO patterned to form active island and contacts. - Source/Drain: 50 nm Mo sputtered and patterned. - Inverted staggered TFT geometry; channel W/L examples: 20/10 µm; arrays from 10/2 to 50/10 µm used for uniformity study. - Control devices: FE-ZAO gated a-IGZO TFTs (ZnO used to induce FE in ZAO then etched; 40 nm a-IGZO sputtered at 200 °C) and MFSM capacitors (Mo/IZO bottom, 40 nm ZAO, 50 nm ZnO, Mo top). - Structural/chemical characterization: - GI-XRD (Rigaku SmartLab) for phase identification (o-, t-, m-, and rhombohedral reflections). - HAADF-STEM (JEOL JEM-ARM200F ACCELARM) with FFT and line profile analysis to extract interplanar spacings and domain orientations; grain size estimation; EDS mapping for elemental distribution. - XPS depth profiling (Thermo Nexsa) to check for contaminants and interface chemistry. - Electrical characterization: - I–V measurements (Agilent 4156C) of IDS–VGS and IG–VGS with forward/reverse sweeps (typically −6 to +6 V) at VDS = 0.1 V unless varied. - MFSM P–V (aixACCT TF3000) and C–V/Loss tangent (Agilent E4980A) at 1 kHz and up to 100 kHz; PUND for 2Pr and Ec. - Memory window (MW) defined at IDS = 10⁻⁶ A; SS extracted in reverse sweep linear regime; Ion/Ioff at 0 V; IG at 0 V. - MW tuning vs VGS amplitude (±2 to ±8 V), vs VDS (0.1–0.7 V), and temperature dependence (25–100 °C). - Multi-level memory pulses: erase −6 V/10 ms; program 2/4/6 V for 10 ms; IDS read at VDS = 0.1 V; retention up to 40,000 s with alternating program/erase sequences. - Synaptic tests: LTP/LTD using non-identical pulse-width series (1→40 ms and 40→1 ms, amplitude 6 V) for 40 conductance states; extraction of nonlinearity (v) using provided equations; Gmax/Gmin. - Neural network simulation: MLP (400-100-10) on MNIST (20×20 pixels), training 8000 images, testing 10,000 images, using measured device parameters; comparison to ideal device.

- Ferroelectric ZAO induced by ZnO growth: - MFSM capacitor (Mo/IZO/ZAO/ZnO/Mo) shows ferroelectric P–V and bowknot-like anti-clockwise C–V hysteresis at 1 kHz. - 2Pr = 15.2 µC/cm² at 10 kHz, 6 V amplitude; PUND yields 2Pr = 13.5 µC/cm² and Ec ≈ 1.1 MV/cm (6 V). Table reports Pr ≈ 7.6 µC/cm² at 41 nm thickness and 360 °C processing. - Unsaturated negative-side P–V attributed to low-frequency defect/leakage effects; loss tangent peaks during ZnO accumulation/depletion consistent with polarization switching. - TFT performance (best at ZAO 40 nm / ZnO 50 nm): - Memory window up to 3.84 V (vs 1.98 V for 50 nm ZAO and 1.38 V for 60 nm ZAO). - Subthreshold swing as low as 55 mV/dec (reverse sweep); Ion/Ioff ≈ 10⁷; off-state current ≈ 1 pA at VDS = 0.1 V. - Gate leakage exhibits butterfly curves with peaks indicative of ferroelectric switching. - MW increases with VGS sweep amplitude (0.98 V at ±2 V to 4.8 V at ±8 V); SS improves to 49 mV/dec at higher VGS; MW saturates near ±8 V. - MW decreases with increasing VDS (0.1→0.7 V) due to reduced switched domain volume near drain. - Temperature: MW decreases from 25→100 °C (domain back-switching via depolarization field), with ON current and IG relatively unchanged; behavior inconsistent with ion migration. - Uniformity: consistent MW and SS across 50 devices with various W/L (10/2 to 50/10 µm). - Structural confirmation of R3m phase in ZAO: - GI-XRD: FE-ZAO shows polycrystalline peaks including o(111), t(011), m(111), m(200); additional shallow peak at 2θ ≈ 30.32° near o(111) indicates R3m (reported ~30.27°). - HAADF-STEM: nanocrystalline ZAO with grain size ~5–15 nm; interplanar spacings d111 = 3.037 Å and d11−1 = 2.927 Å; angle ≈71.7° between [111] and [11−1], consistent with polar rhombohedral R3m; growth at both bulk and interfaces. - ZnO shows wurtzite phase (d002 = 0.259 nm) and higher CTE than ZrO2/Al2O3; estimated compressive strain induced in ZAO by ZnO ≈ 968 MPa. - Multi-level memory and neuromorphic metrics: - Programmable multi-level IDS with VGP = 2/4/6 V (10 ms) yields on/off ratios after 4000 s of 1.1×10⁵, 1.3×10⁶, and 3.4×10⁷, respectively; off-state IDS ≤ 10 pA after each erase. - Retention: on/off ratio 1.3×10⁷ after 40,000 s at VDS = 0.1 V. - Synaptic behavior: 40 analog conductance states with Gmax/Gmin ≈ 21.67; nonlinearity vLTP ≈ −0.25, vLTD ≈ 0.33; Gmax ≈ 1.97×10⁻⁷ S, Gmin ≈ 9.10×10⁻⁸ S. - MLP simulation (400-100-10) on MNIST achieves 91.82% accuracy using device parameters vs 94.65% for an ideal device.

The data demonstrate that compressive strain from a ZnO overlayer can crystallize amorphous ZAO into a polar rhombohedral R3m phase, enabling robust ferroelectricity in relatively thick (~40 nm) films processed at moderate temperature by spray pyrolysis. The observed anti-clockwise hysteresis in IDS–VGS, butterfly IG–VGS with switching peaks, large memory windows, and sub-60 mV/dec SS corroborate ferroelectric gating behavior. GI-XRD and HAADF-STEM unambiguously confirm the R3m phase with characteristic interplanar spacings and domain orientations. Electrical dependencies support ferroelectric origin: MW scales with VGS amplitude, decreases with VDS due to reduced switched domain volume near the drain, and diminishes with temperature due to depolarization-driven back-switching rather than ionic effects. The devices exhibit uniform characteristics across geometries, low leakage, and stable retention, enabling reliable multi-level states. In neuromorphic operation, low nonlinearity and a sizable dynamic range translate into high simulated learning accuracy (91.82%), approaching ideal synaptic behavior. Together, these results validate strain-engineered ZAO as a CMOS-abundant, thicker-film ferroelectric suitable for multi-level memory and neuromorphic computing.

The study introduces a spray-pyrolyzed ZAO gate insulator that becomes ferroelectric through compressive strain induced by ZnO growth, stabilizing the polar R3m phase at ~40 nm thickness. MFSM capacitors exhibit strong ferroelectric responses (2Pr up to 15.2 µC/cm²; Ec ≈ 1.1 MV/cm) and characteristic C–V hysteresis. ZAO-gated ZnO TFTs deliver a large memory window (3.84 V), sub-60 mV/dec subthreshold swing, Ion/Ioff ≈ 10⁷, and ~pA off-current. Multi-level programmability, long retention (on/off 1.3×10⁷ at 40 ks), and analog synaptic characteristics (low LTP/LTD nonlinearity, Gmax/Gmin ≈ 21.67) yield high neural-network accuracy (91.82%). These findings establish strain-stabilized ZAO as a promising, low-power, and cost-effective platform for next-generation multi-level memory and neuromorphic electronics. Future work could explore integration on silicon platforms, endurance/cycling performance, and further optimization of strain engineering and defect control to enhance saturation and temperature stability.

- P–V loops show unsaturated behavior on the negative bias side at low frequency, attributed to defect state excitation and leakage in the ZAO/ZnO stack. - Polarization relaxation at 0 V is observed in MFSM structures, more pronounced than in MFM, which may affect intermediate state stability. - Memory window decreases with increasing temperature (25–100 °C) due to depolarization-induced back-switching and with increasing VDS due to reduced switched domain volume; these dependencies may constrain operating conditions. - Ferroelectric phase formation requires sufficient ZnO thickness to induce adequate compressive strain; device performance is therefore sensitive to stack design. - Demonstrations are on glass/Mo substrates; direct CMOS/Si integration and endurance/cycling characteristics were not reported here.