Spiking neurons from tunable Gaussian heterojunction transistors

The study addresses the challenge of implementing energy-efficient spiking neural networks in hardware. Conventional CMOS technologies do not intrinsically reproduce the time-dependent conductance of ion channels in biological neurons, requiring complex multi-transistor circuits that limit very-large-scale integration density. Digital neuromorphic platforms multiplex neurons due to area constraints, reducing biological parallelism. The authors propose using low-dimensional materials to realize device-level neuromorphic functionality. They hypothesize that dual-gated Gaussian heterojunction transistors (GHeTs), based on mixed-dimensional van der Waals heterostructures of monolayer MoS2 and semiconducting carbon nanotube networks, can provide fully tunable antiambipolar (Gaussian) transfer characteristics suitable for emulating sodium and potassium ion channel dynamics. The goal is to simplify spiking neuron circuits while enabling multiple biologically relevant spiking modes with improved electrostatic control and scalability.

Prior neuromorphic hardware efforts have primarily focused on synaptic devices such as memristors, memtransistors, domain-wall memories, metal-insulator-transition devices, multi-gated transistors, and Gaussian synapses to achieve scalable synaptic functions. Implementations of spiking neurons are fewer and face limitations: neuristors based on MIT devices suffer from low gain and limited output swing; diffusive memristors with capacitors can spike but lack biophysical spike characteristics and runtime adaptation; leaky integrate-and-fire neurons combining memristors with CMOS still require many circuit elements; magneto-electric neuron proposals dissipate energy continuously; ferroelectric FET neurons provide only spike frequency adaptation and are temperature sensitive; photonic neurons based on phase-changing materials offer speed and bandwidth but lack biophysical features. Single-gated antiambipolar heterojunctions from 2D and organic materials have been used in analog processing, logic, and photodetection, but lack sufficient tunability of the Gaussian transfer function for efficient neuromorphic implementation. Mixed-dimensional van der Waals heterostructures provide weak electrostatic screening and gate-tunable properties, motivating the dual-gated architecture explored here.

Device design and fabrication: The GHeTs use a mixed-dimensional van der Waals heterojunction comprising CVD-grown monolayer MoS2 (n-type) and solution-processed semiconducting single-walled carbon nanotube (CNT) networks (p-type/ambipolar). A photolithography-based self-aligned, semi-vertical dual-gate process was adapted for wafer-scale fabrication. Key steps: (1) Pattern local bottom gates (10 nm Cr/10 nm Au/4 nm Al) on undoped Si/300 nm SiO2, followed by ~35 nm Al2O3 by ALD at 100 °C; the thin Al layer seeds ALD on Au. Resist undercut and directional evaporation plus conformal ALD create encapsulated metal with a self-aligned dielectric extension (~300 nm measured by AFM). (2) Transfer monolayer MoS2 (grown by solid-precursor CVD on sapphire) via polycarbonate-assisted wet transfer onto the bottom gates; pattern MoS2 using a PMGI/S1813 bilayer and Ar RIE (50 sccm, 13.3 Pa, 50 W, 20 s). (3) Form self-aligned encapsulated bottom contacts on MoS2 (4 nm Ti/40 nm Au/4 nm Al plus 35 nm Al2O3). Protect MoS2 regions that should not be overlapped by CNTs with ~5 nm ALD Al2O3 mask. (4) Deposit top contacts (10 nm Cr/70 nm Au) atop encapsulated bottom contacts. (5) Transfer a density-optimized (~10 tubes/µm) 99% semiconducting P2 CNT network (density gradient ultracentrifugation) by vacuum filtration on cellulose membrane and acetone-bath transfer overnight; pattern CNTs by S1813 and O2 RIE (20 sccm, 26.5 Pa, 100 W, 15 s). A thin S1813 residue intentionally remains to encapsulate CNTs and minimize ALD-induced doping. (6) Deposit ~35 nm ALD Al2O3 over the entire device; pattern local top gates (10 nm Cr/60 nm Au) overlapping the junction region. The resulting semi-vertical dual-gated architecture supports multiple current paths and enhanced electrostatic control.

Materials and electrical characterization: Layer thicknesses were measured by AFM (Asylum Cypher) in ambient. Electrical measurements were performed in ambient at room temperature on a Cascade MicroTech probe station using a Keithley 4200 analyzer. Control dual-gated MoS2 and CNT transistors (50 µm width) verified n-type and ambipolar behavior, respectively, with dual-gate threshold tunability.

GHeT characterization: Independent gate biasing (holding one gate constant while sweeping the other) showed gate-tunable rectifying diode behavior and a Gaussian antiambipolar transfer curve. Top-gate sweep at VBG = 0 V modulated rectification polarity via band-to-band tunneling. Rectification ratio (ID at VD=1 V divided by ID at VD=-1 V) was tunable by both VTG and VBG by over two orders of magnitude; rectification direction reverses for VTG > 2 V. The antiambipolar peak position in ID–VTG could be shifted from ~2 V to −3 V by varying VBG. Transconductance analysis indicated the top gate fully modulates CNTs and partially modulates MoS2 through the CNT film; the bottom gate fully modulates MoS2 but not the CNTs due to screening by the continuous MoS2 layer, implying current predominantly flows in the overlap region.

Dependent gate biasing (simultaneous sweeping of VTG and VBG with a fixed offset) combined top- and bottom-gate modulation, yielding full control over the Gaussian response. With equal oxide thickness (~35 nm) on both gates, equivalent fields are achieved for equal biases. By varying VTG−VBG from 3 V to −3 V, the Gaussian peak position shifted from −3 V to 0.5 V while maintaining symmetry and peak current. Device statistics over a 0.5 × 0.5 cm area showed 85% of devices exhibited Gaussian transfer responses (VTG−VBG = 0 V), with average peak position ~0.42 V ± 0.55 V and average FWHM 2.92 V ± 0.48 V. VD modulation at fixed dependent bias controlled peak height with minimal change in peak position and FWHM; adjusting both VD and VTG−VBG tuned peak position while maintaining height and FWHM. Switching between dependent and independent gate operation modulated FWHM while maintaining peak height and position.

Spiking neuron circuit: A Hodgkin–Huxley-inspired neuron was implemented using one MoS2–CNT GHeT and two n-type FETs (T1, T2) plus passive elements (R1, R2, C1, C2). The circuit maps GHeT antiambipolar dynamics to the sodium channel conductance gNa and uses a delayed NMOS turn-on to emulate potassium channel conductance gK. Experimental parameters: V1=4 V, V2=1 V, V3=230 mV, V4=3 V, V5=280 mV; R1=100 kΩ, R2=1 MΩ; C1=440 nF, C2=220 nF; Isyn offset I0=1 nA; commercial transistors BSR802N. Measurements were taken in ambient at room temperature. Circuit simulations were performed in Cadence Virtuoso (Spectre) using a Verilog-A LUT model calibrated to experimental transport of GHeTs and commercial FETs; other elements from Virtuoso Analog library. Additional simulated circuits introduced independent gate biasing and modest logic elements (inverter, diode, Schmitt trigger) to realize multiple spiking modes.

• Dual-gated mixed-dimensional MoS2–CNT GHeTs exhibit fully tunable Gaussian (antiambipolar) transfer characteristics. Independent gate operation tunes diode rectification ratio by >2 orders of magnitude and can invert rectification polarity (VTG sweep at VBG=0 V).
• Dependent gate operation enables symmetric Gaussian tuning: shifting peak position by ~3.5 V (VTG−VBG from 3 V to −3 V) with minimal loss in peak current. Peak height, peak position, and FWHM can be independently modulated via VD, VTG−VBG, and switching between dependent/independent biasing.
• Wafer-scale fabrication yields high device functionality: 85% of devices over 0.5 × 0.5 cm show Gaussian transfer; average peak position ~0.42 V ± 0.55 V (for VTG−VBG = 0 V) and average FWHM 2.92 V ± 0.48 V.
• A compact spiking neuron circuit using a single GHeT, two NMOS transistors, two capacitors, and two resistors reproduces Hodgkin–Huxley-like dynamics, with experimentally observed constant spiking; spike temporal FWHM ~200 ms. Cadence simulations closely match experimental spiking traces.
• Energy consumption per spike for the demonstrated circuit is ~250 nJ, with clear pathways for reduction (device scaling, capacitance reduction, thinner gate dielectrics, integrated custom transistors).
• The antiambipolar response (both negative and positive transconductance regions near IPEAK) is necessary for sustained spiking; adjusting gate offsets controls spiking behavior.
• Simulations demonstrate multiple biologically relevant spiking modes achievable with modest circuit variations and gate-bias schemes: constant spiking, Class-I frequency increase with Isyn, spike latency, integrator behavior, phasic spiking, phasic bursting, tonic bursting, and dampened tonic bursting.

The results validate the premise that a dual-gated Gaussian heterojunction transistor can intrinsically emulate key aspects of neuronal ion-channel dynamics, enabling simpler spiking neuron circuits than conventional CMOS-only implementations. Full electrostatic control over the Gaussian transfer function—independently tuning peak height, position, and FWHM—allows mapping to the time-dependent conductance of the sodium channel (gNa), while a delayed NMOS activation emulates the potassium channel (gK). The experimental neuron exhibits sustained spiking with pulse widths in the hundreds of milliseconds, confirming the feasibility of device-level neuromorphic behavior. The approach significantly reduces circuit element count for multiphenomenology spiking neurons and offers runtime programmability of spiking thresholds and modes via gate-bias control. Beyond neuromorphic computing, the native and tunable Gaussian response of GHeTs can simplify hardware implementations of algorithms requiring Gaussian functions, such as Gaussian mixture models in speech processing, Bayesian neural networks, and Gaussian filtering in computer vision, overcoming complexity and programmability limits of CMOS analog/digital realizations.

This work demonstrates wafer-scale, dual-gated MoS2–CNT Gaussian heterojunction transistors with unprecedented electrostatic tunability of Gaussian transfer curves and leverages them to realize compact, biomimetic spiking neuron circuits. The devices enable independent control of peak height, position, and FWHM, and achieve high functional yield across a large area. A minimal circuit with a single GHeT reproduces Hodgkin–Huxley-like spiking experimentally, and simulations show a rich set of additional spiking behaviors achievable with modest circuit adjustments. The fabrication is compatible with previously demonstrated MoS2 memtransistor synapses, supporting scalable neuromorphic platforms. Future work should focus on reducing energy per spike and increasing speed via device scaling (narrower channels), lower capacitances, thinner dielectrics, and monolithic integration of auxiliary transistors; integrating arrays for large-scale spiking neural networks; and exploring broader AI hardware applications that benefit from programmable Gaussian responses.

• The experimentally demonstrated spiking neuron exhibits relatively slow dynamics (~200 ms spike FWHM) and energy per spike of ~250 nJ; improvements require device and circuit scaling (reduced C1/C2, thinner dielectrics, smaller channel widths) and custom on-chip integration of T1/T2.
• Some demonstrated spiking modes (e.g., phasic and tonic bursting, integrator, spike latency) are shown in simulations; only constant spiking is experimentally validated in this work.
• Independent gate control is partially limited by electrostatic screening: the bottom gate cannot fully modulate the CNT network due to screening by the MoS2 monolayer, and the top gate cannot fully deplete MoS2 for certain VBG, affecting independent bias tunability.
• Reported device statistics (peak position, FWHM) are based on 14 devices exhibiting Gaussian response within a 0.5 × 0.5 cm area; broader variability, long-term stability, and environmental robustness are not extensively characterized.
• The neuron circuit still relies on external NMOS transistors and passive components; full integration will require additional process development.