Neuromorphic device based on silicon nanosheets

Artificial neural network (ANN) is a computation paradigm enabling concurrent processing and machine learning, useful for classification, image processing, and natural language processing. However, von Neumann architectures suffer from latency due to memory-processor data movement, motivating in-memory computing devices such as memristors for ANN. Biological neural networks transmit event-driven discrete spikes, unlike most ANN implementations using continuous-valued signals, motivating spiking neural networks (SNNs) that more closely mimic the nervous system by using spike timing and rate information. Realizing efficient SNN hardware requires novel synaptic devices and circuits capable of processing discrete spikes. Many neuromorphic devices have been developed using organic semiconductors, quantum dots, and other emerging materials, but their mechanisms (e.g., interface trap-induced effects) can be elusive and less controllable. Materials compatible with Si technology and with well-understood neuromorphic behavior are needed. Two-dimensional materials offer tunable electronic properties for device design. Silicon nanosheets (SiNSs), 2D thin films of Si with different crystal structures than bulk Si, are promising due to potential Si-technology compatibility and distinct properties (large, quasi-direct bandgap). This work investigates whether self-assembled, partially oxidized, surface-modified SiNS stacks can serve as multifunctional neuromorphic elements exhibiting memristive and synaptic behaviors compatible with CMOS processes, and elucidates the underlying charge-storage/Schottky-junction mechanism for SNN applications.

The paper situates its work within neuromorphic computing research: prior ANN/SNN hardware accelerators leverage memristors and other in-memory devices but often rely on mechanisms such as conductive filaments, ion migration, or interface traps that can be difficult to control. Devices based on organic semiconductors and quantum dots have been explored but face stability and mechanism-clarity challenges. Two-dimensional materials have enabled fine-tuning of electronic properties for device engineering. Silicon nanosheets, distinct from bulk Si and potentially CMOS-compatible, have shown large and quasi-direct bandgaps in prior studies, suggesting opportunities for optoelectronics and neuromorphic functions. The work builds on these insights to propose SiNS-based devices with controllable, well-modeled behavior arising from capacitive charge storage in partially oxidized stacks coupled with Au–Si Schottky junctions.

Material preparation: Saturated HCl-in-ethanol was prepared by bubbling HCl (generated from NaCl and H2SO4) through 50 mL ethanol. CaSi2 crystallites (~0.5 g) were immersed in 50 mL of this ethanol HCl solution in a Schlenk flask and stirred under N2 for 3 days to exfoliate and obtain H-terminated SiNSs. The mixture was filtered on a Schlenk line. The residue was transferred into 50 mL p-fluoroaniline (PFA) and stirred for 7 days under N2 (reported at room temperature in Methods) to perform surface modification; the product was collected and stored in N2. The PFA capping suppresses oxidation via steric hindrance, increases n-type carrier density through electron donation from PFA’s N lone pairs, provides interlayer π–π interaction and hydrogen bonding to promote hierarchical stacking and electron hopping, and improves solution processability, enabling uniform films on nonpolar substrates (e.g., PET, Si, silane-treated SiO2/Si).

Device fabrication: Substrates were heavily p-doped <100> Si with 200 nm SiO2, diced to 1×1 cm2. Surfaces were rendered nonpolar by immersion in toluene solution of (3-aminopropyl)trimethoxysilane at 60 °C for 4 min in N2, followed by solvent rinses and drying. The active layer was formed by dropping 80 µL of the SiNS/PFA mixture; after PFA solvent evaporation, thermal annealing was performed on a hot plate at 100 °C for 10 min (moderate) or 200 °C for 30 min (sufficient) in N2. Gold electrodes (120 nm) were thermally evaporated through a shadow mask, defining channels 100 µm long and 1000 µm wide.

Characterization: Structure and composition were characterized by XRD (SHIMADZU LabX XRD6000, Cu Kα), HRTEM (JEM 2100F, 200 kV), FTIR (JASCO FT/IR-6100), XPS (Kratos AXIS Ultra DLD), UPS (Thermo ESCALAB 250Xi, He I 21.2 eV). Optical properties were measured by PL (Edinburgh F920; transient PL excited at 280 nm, 50 Hz) and UV–Vis–NIR absorption (HITACHI U-4100). Electrical properties: Hall measurements (Lakeshore 7604) assessed conductivity type, carrier density, and mobility. Device electrical tests used a semiconductor parameter analyzer (FS480, PDA Co. Ltd.). Quasi-static I–V scans used 100 evenly spaced points between 0 and Vmax with 0.04 s point interval; I–t spike tests used 1 V spikes of 1 s duration with 0.04 s sampling.

Modeling and simulations: A compact circuit model comprises a large stack capacitance (CNSS) from partially oxidized, hierarchical SiNS stacks, series stack resistance (RNSS), and Schottky contact resistance (Rcon) at Au/SiNS interfaces. Under small biases, Rcon is treated as constant; at higher biases, Rcon varies due to Schottky barrier breakdown, avalanche/tunneling currents, and resulting negative differential resistance (NDR). Analytical expressions describe hysteretic I–V behavior at low bias; parameters CNSS, RNSS, and Rcon were extracted by fitting. Simulink (Matlab R2020a) simulations modeled quasi-static I–V and synaptic behaviors using parameters consistent with experiments (e.g., RNSS ~1×10^6–10^9 Ω depending on condition, Rcon ~6×10^7 Ω, CNSS ~10^−7–10^−6 F). SNN simulations for MNIST classification used device-measured STDP patterns to drive unsupervised learning under three encoding regimes: S1 (potentiation-only), S2 (potentiation+depression), and S3 (potentiation-only with high-voltage-induced initial inverse response due to NDR).

• Material structure and properties: XRD and HRTEM show SiNSs with new crystalline phases distinct from bulk Si and CaSi2, with graphene-like arrangements and inferred ABC stacking. Strong PL observed with deep-UV excitation (~280 nm) and emission (~350 nm), with short lifetime (~0.7 ns), consistent with quasi-direct bandgap; bandgap estimated ~3.2–3.5 eV. UV–Vis shows resonance absorption at PL wavelengths. UPS indicates work function ~4.06 eV and Fermi level ~3.10 eV above valence band edge (n-type). Hall data reveal n-type conductivity attributed to PFA-induced electron donation, carrier density ~2.5 × 10^15 cm^−3, and mobility ~300 cm^2 V^−1 s^−1 (about an order higher than reported for single-layer silicene). Films are ~15 µm thick with bundles ~20 nm thick.
• Device mechanism: Au contacts (work function ~5.1 eV) form back-to-back Schottky junctions with SiNSs; Schottky barrier ~1.04 eV. Partially oxidized, hierarchical SiNS stacks provide large capacitance (CNSS). The coupled CNSS and Schottky junctions produce hysteresis and memristor-like behavior distinct from filamentary/ionic mechanisms.
• Annealing dependence: Sufficient annealing (200 °C, 30 min) lowers RNSS (and oxidation), effectively shorting CNSS and yielding symmetric, non-hysteretic back-to-back Schottky I–V. Moderate annealing (100 °C, 10 min) increases RNSS and Rcon due to partial oxidation; hysteresis appears due to large CNSS.
• Parameter extraction at low bias (≤1 V): Fitting the constant-contact model yields CNSS ≈ 7 × 10^−7 F, RNSS ≈ 1 × 10^6 Ω, Rcon ≈ 6 × 10^7 Ω; a geometric estimate gives CNSS ≈ 1 × 10^−7 F, comparable in order of magnitude.
• High-bias behavior and unipolar memristor: Increasing scan voltage induces varying Rcon due to Schottky breakdown and NDR. The NDR reduces junction voltage Ucon while total current rises, boosting voltage across CNSS (UNSS) and triggering a large charging current (LRS). As CNSS charges, current decays quasi-exponentially to HRS; upon voltage return to 0, the device remains HRS due to stored charge reducing barrier height. On voltage reversal, the same behavior occurs, yielding unipolar switching. LRS/HRS differ by >1 order of magnitude; cycles overlap well, indicating reversible, non-filamentary operation.
• Synaptic behaviors (low-voltage spikes, 1 V): Devices exhibit depression (habituation) under repeated same-polarity spikes as CNSS charges; paired-pulse depression increases with inter-spike interval. Opposite-polarity spikes reset sensitization immediately by depleting stored charge; back-gate positive spikes (1 V) can reset without overcompensation by enhancing Schottky depletion-region tunneling. Long-term memory (LTM) follows quasi-exponential dependence on spike count, consistent with analytical model. Spike timing-dependent plasticity (STDP) and spike rate-dependent plasticity (SRDP) are demonstrated experimentally; deviations from simulations arise from frequency-dependent CNSS and non-constant contact impedance.
• Generality: Behavior reproduced on PET substrates and emulated with commercial components; some non-idealities (e.g., first I–V loop differs from subsequent loops) noted.
• SNN simulations (MNIST): Using measured STDP patterns, unsupervised SNN achieves overall accuracies of 88.50% (S1), 92.80% (S2), and 91.50% (S3). S2 (bi-directional STDP) improves edge contrast and category-wise accuracy (>80% for all digits). S3 (with initial inverse response due to NDR) shows superior noise robustness: under Gaussian noise (variance 0.01–0.04), S3 accuracy degrades less than S1; visualized synapses for S3 better filter noise and retain digit fidelity.

The study addresses the challenge of realizing controllable, CMOS-compatible neuromorphic devices for SNNs by leveraging surface-modified, partially oxidized silicon nanosheet stacks. The hierarchical stacking yields large intrinsic capacitance, while Au–SiNS interfaces form Schottky junctions. Their coupling explains observed hysteresis, unipolar memristor-like switching, and synaptic plasticity without reliance on ionic migration or filament formation. Analytical and numerical models capture low-bias hysteresis and spike-driven LTM/STDP behaviors, linking device physics (CNSS, RNSS, Rcon, Schottky barrier modulation) to neuromorphic functions. The demonstrated SNN simulations show that device-specific STDP patterns can be exploited for unsupervised learning, with bi-directional STDP enhancing recognition accuracy and NDR-enabled inverse response improving noise tolerance. These results highlight the significance of re-centering silicon in neuromorphic hardware through a mechanism compatible with established processing, potentially easing integration with CMOS and enabling scalable, energy-efficient SNNs.

This work introduces a multifunctional neuromorphic device platform based on PFA-modified silicon nanosheet stacks that self-assemble into hierarchical structures. The devices exhibit unipolar memristor-like switching via Schottky NDR–capacitance coupling and synaptic behaviors (LTM, STDP, SRDP) with fast, low-voltage reset. A compact model quantitatively explains device operation, and SNN simulations demonstrate effective digit recognition and enhanced noise filtering using device-derived STDP. The approach brings silicon back to the forefront for neuromorphic computing with potential CMOS compatibility. Future research directions include: (1) exploiting SiNS photoemission for optoelectronic neuromorphic components; (2) developing flexible, solution-processed devices on soft substrates; and (3) fabricating CMOS-compatible SNN arrays to bridge AI hardware with mature Si industry processes.

• Device-to-device and cycle-to-cycle non-idealities: the first I–V loop can differ from subsequent loops; circle-to-circle coherency requires improvement.
• Model deviations: constant-contact and fixed-capacitance assumptions break down at higher fields/frequencies; CNSS and contact impedance vary with excitation conditions, causing discrepancies in STDP/SRDP fits.
• Partial oxidation control: performance depends on controlled partial oxidation and annealing; optimizing stack uniformity and contact interfaces is ongoing.
• Performance metrics: while proof-of-concept is shown, endurance, retention, operating speed, energy per spike, and large-scale array uniformity were not comprehensively optimized or reported.
• Temperature/processing inconsistencies between schematic and methods may require process standardization for reproducibility.