Magnetic memory driven by topological insulators

Non-volatile magnetic random-access memory (MRAM) stores information via the resistance states of magnetic tunnel junctions (MTJs). Spin-orbit torque (SOT) enables efficient current-driven switching and, in a 3-terminal geometry, improves endurance by keeping write current out of the MTJ barrier. However, energy consumption remains a challenge because classical heavy-metal-based SOT systems have charge–spin conversion efficiency θ_SH < 1, requiring high current densities (~10^7 A cm^−2). Topological insulators (TIs) offer spin-momentum-locked surface states with potentially θ_SH > 1 at room temperature, but integrating single-crystal TI layers with MTJs compatible with CMOS processing is difficult due to epitaxial growth needs, interfacial control, diffusion during annealing, and chemical degradation during lithography. This work addresses these integration challenges by realizing a TI-driven SOT-MRAM cell that simultaneously achieves a state-of-the-art TMR (>100%) and ultralow switching current density (~10^5 A cm^−2) at room temperature, and quantifies θ_SH > 1 using two independent methods.

Prior work established SOT-driven switching in heavy metal/ferromagnet systems with typical current densities ~10^7 A cm^−2. Quantum materials, notably topological insulators, have been predicted and experimentally shown to exhibit large charge–spin conversion due to spin-momentum locking of surface Dirac states, with θ_SH reported to exceed that of heavy metals even at room temperature. Demonstrations of SOT from TIs include magnetization switching and ST-FMR measurements in TI/FM bilayers. Nonetheless, translating these effects into functional MTJ-based devices has been hindered by materials integration issues: epitaxial TI growth on non-CMOS substrates, interfacial quality required for high TMR, element interdiffusion during MTJ annealing that can degrade TI surface states, and susceptibility of TIs to processing chemicals. The present study builds on this literature by integrating a TI with an MgO-based MTJ, achieving both high TMR and low-current SOT switching, and by benchmarking θ_SH via device-level and ST-FMR methods.

Device design and stack: The TI–MTJ stack is (BiSb)2Te3(10 nm)/Ru(5 nm)/CoFeB(2.5 nm)/MgO(1.9 nm)/CoFeB(5 nm)/Ta(8 nm)/Ru(7 nm). The Ru interlayer decouples exchange between the TI and CoFeB and blocks diffusion during annealing. MTJs are patterned atop the TI bottom electrode to form 3-terminal SOT devices. Annealing at 300 °C for 1 h under an 8 kOe in-plane magnetic field improves MgO crystallinity/TMR and sets in-plane easy axes in both CoFeB layers. Growth and fabrication: (Bi1−xSbx)2Te3 films (10 nm) are grown epitaxially on Al2O3(0001) by MBE in ultrahigh vacuum with layer-by-layer RHEED-monitored growth. Substrates are pre-annealed up to 700 °C. Bi (457 °C), Sb (387 °C), and Te (340 °C) sources are co-evaporated while maintaining substrate at 200 °C. MTJ layers are deposited by magnetron sputtering (base pressure ~1 × 10^−6 Pa) at room temperature; Co40Fe40B20 layers are sputtered under a 50 Oe in-plane field. Patterning uses photolithography and electron-beam lithography with two Ar ion milling steps; a 300 nm PMMA protective layer shields the TI from developer chemicals and is removed by O2 plasma prior to milling. Device geometry and measurements: The TI serves as the bottom SOT channel (terminals T1–T2 for write), with the MTJ (typical mesa sizes from 4 μm × 8 μm down to 100 nm × 200 nm) located at the overlap with a top electrode; read current is applied vertically through the MTJ (terminals T1–T3). SOT switching tests use 1 ms current pulses for write (between T1–T2), followed by 10 μA, 1 ms read pulses through the MTJ 1 s later. Two configurations are studied: collinear spin polarization and magnetic easy axis (σ || EA, EA along y) enabling field-free switching, and orthogonal (σ ⊥ EA, EA along x) requiring a small external in-plane bias field for deterministic switching. Magnetic properties are characterized by VSM. SOT quantification via switching field shift: With EA along y, a dc bias current in the TI channel shifts the coercive field H_c2 of the bottom CoFeB in R–H loops. The SOT effective field H_SOT is extracted from the bias-dependent shift H_shift = (H_c2+shift − H_c2−shift)/2 = H_SOT(J_c). The slope χ_SOT = H_SOT/J_c yields θ_SH via θ_SH = (2|e| M_s t_p / ħ) χ_SOT using M_s = 1100 emu cm^−3 and t_p = 2.5 nm. SOT quantification via ST-FMR: For (BiSb)2Te3(10)/Ru(5)/CoFeB(2.5)/MgO(1.9), a microwave current (12 dBm) drives FMR with in-plane field at 45°. The mixed dc voltage V_mix is fitted to extract symmetric (S, SOT-related, proportional to current density in TI) and antisymmetric (A, Oersted-field-related, dominated by Ru-layer current) components. After subtracting a spin pumping contribution (27% of S), θ_SH is computed from the S/A ratio with known layer thicknesses and effective magnetization (4πM_eff ≈ 1.19 T from Kittel fits). All-sputtered variant: To assess manufacturability, BiSb(10 nm) is prepared by magnetron sputtering, followed in situ by Ru(5)/CoFeB(2.5)/MgO(2)/CoFeB(5)/Ta(8)/Ru(7) without vacuum break. SOT switching and TMR are characterized similarly.

- Functional TI–MTJ SOT-MRAM cell realized with room-temperature TMR = 102% and ultralow critical switching current density J_c = 1.2 × 10^5 A cm^−2 (σ || EA, field-free configuration). - Two switching modes: collinear σ || EA yields field-free deterministic switching with simulated switching time ~7.5 ns; orthogonal σ ⊥ EA requires bias field (~±100 Oe) but achieves faster simulated switching (~1.0 ns). In the orthogonal case, J_c ≈ 4.1 × 10^5 A cm^−2. - Scaling MTJ dimensions from micrometers to nanometers mitigates domain pinning from TI surface steps: near-full SOT switching achieved for 100 × 200 nm^2 (ΔTMR/TMR ≈ 95%) and 150 × 300 nm^2 (≈92%) MTJs, consistent with (BiSb)2Te3 surface grain sizes (~200–300 nm). - SOT effective field vs current: χ_SOT = H_SOT/J_c = 24.1 × 10^−6 Oe A^−1 cm^2; corresponding θ_SH = 1.59 using M_s = 1100 emu cm^−3 and t_p = 2.5 nm. Interfacial efficiency θ_ICS = θ_SH/t_i ≈ 1.06 nm^−1 for TI surface thickness t_i ≈ 1.5 nm. - ST-FMR on (BiSb)2Te3(10)/Ru(5)/CoFeB(2.5)/MgO(1.9) yields frequency-independent θ_SH ≈ 1.02 (after subtracting 27% spin pumping contribution) over 5–8 GHz, consistent with the switching-field method. Extracted 4πM_eff ≈ 1.19 T. - All-sputtered BiSb–MTJ devices exhibit TMR ≈ 90% and SOT switching with J_c ≈ 1.4 × 10^6 A cm^−2 at room temperature. Higher conductivity of sputtered BiSb (~1.8 × 10^5 Ω^−1 m^−1) may reduce ohmic losses due to shunting. - Integration strategy (Ru interlayer, optimized annealing, TI surface protection during lithography) preserves TI surface states and MTJ quality, enabling simultaneous high TMR and low-current SOT switching.

The study directly addresses the central challenge of integrating topological insulators with high-performance MTJs for practical SOT-MRAM. By engineering the TI/MTJ interface (Ru interlayer to suppress exchange coupling and diffusion) and protecting the TI during processing, the authors achieve a state-of-the-art TMR exceeding 100% while maintaining the TI’s large spin–momentum-locked surface contribution to SOT. The demonstrated ultralow J_c (1.2 × 10^5 A cm^−2) in the field-free σ || EA configuration dramatically lowers the write energy compared with heavy-metal-based SOT devices. Independent quantification methods—SOT-induced coercive field shifts and ST-FMR—both yield θ_SH > 1 at room temperature (1.59 and 1.02), validating that TI surface states can overcome the classical θ_SH < 1 limit and are effective in a full MTJ device context. Device scaling mitigates domain pinning from TI surface steps, enabling nearly full switching in sub-300 nm MTJs, which aligns with observed TI grain sizes and informs scaling requirements for arrays. While the orthogonal configuration requires a small bias field, it provides a faster switching trajectory (~1 ns), suggesting a performance–assist-field tradeoff. The all-sputtered BiSb–MTJ demonstrates a path toward industry-compatible fabrication, albeit with higher J_c than MBE-grown TI, and highlights the benefit of higher channel conductivity for reducing ohmic losses. Overall, the results substantiate TIs as viable SOT sources for low-energy MRAM and provide practical engineering guidelines for materials integration and device architecture.

A TI-driven SOT-MRAM cell integrating a high-quality MgO-based MTJ with an epitaxial (BiSb)2Te3 bottom electrode demonstrates room-temperature TMR > 100% and ultralow switching current density down to 1.2 × 10^5 A cm^−2. The TI’s charge–spin conversion efficiency exceeds unity, verified by both switching-field-shift (θ_SH ≈ 1.59) and ST-FMR (θ_SH ≈ 1.02) methods. Field-free switching is achieved in the collinear σ || EA configuration, while the orthogonal configuration offers faster switching with modest field assistance. Scaling studies show near-complete SOT switching in sub-300 nm MTJs, consistent with TI surface grain sizes. An all-sputtered BiSb–MTJ variant exhibits ~90% TMR and J_c ~ 1.4 × 10^6 A cm^−2, indicating feasibility for CMOS-compatible processing. These advances lay the groundwork for low-energy, high-endurance SOT-MRAM based on quantum materials and suggest further optimization of sputtered TI films, interfacial engineering, and device scaling for future commercial deployment.

- Partial SOT switching in larger (micrometer-scale) MTJs due to magnetic domain pinning from (BiSb)2Te3 surface steps necessitates device scaling to sub-300 nm for near-full switching. - The orthogonal σ ⊥ EA configuration requires an external bias field for deterministic switching, which may complicate field-free operation unless alternative symmetry-breaking schemes are used. - All-sputtered BiSb devices exhibit higher J_c (by ~1 order of magnitude) than MBE-grown TI counterparts, indicating room for materials/process optimization to reduce write current. - TI integration requires careful diffusion blocking and chemical protection during fabrication; deviations could degrade TI surface states or MTJ performance.