Machine learning enables completely automatic tuning of a quantum device faster than human experts

Quantum dots are promising for scalable quantum computation and simulation because they can be electrically controlled and are compact compared to superconducting qubits. These devices operate as transistors in which electrons are controlled by applied gate voltages; correctly setting these voltages creates single and double quantum dots that enable single-electron control and spin qubits. However, device variability due to charge traps and defects means that the required combination of gate voltages to form a double quantum dot varies between devices and even after thermal cycling. This variability, alongside a high-dimensional gate-parameter space, makes manual tuning time-consuming and increasingly impractical for arrays of devices. The study addresses the problem of automatic "coarse tuning"—finding regions in multidimensional gate-voltage space that render a device operational—by introducing a machine learning algorithm that efficiently searches up to eight-dimensional gate spaces to locate transport features (Coulomb peaks and honeycomb patterns) indicative of operational single/double quantum dot regimes.

The paper positions its approach alongside prior experimental and algorithmic advances in quantum dot control and spin qubit tuning. It references established work on coherent manipulation of coupled spins in semiconductor quantum dots and recent efforts in automated or learning-based tuning for semiconductor spin qubits. Alternative measurement techniques such as charge sensing and dispersive readout are acknowledged but noted to require additional parameter optimization. The authors emphasize that previous coarse tuning approaches required substantial manual input or were constrained to small subspaces, motivating a more general, data-efficient, and minimally-assumptive algorithm.

The algorithm targets automatic tuning in gate-defined double quantum dot devices implemented in a GaAs/AlGaAs 2DEG with Ti/Au gates. It assumes only that (i) relevant transport features lie near a boundary hypersurface that separates low-current (pinched-off) and high-current regions in gate-voltage space, and (ii) large areas of this hypersurface do not exhibit transport features. The overall pipeline alternates between a sampling stage and an investigation stage. - Initialization: Set V_bias. Measure current at two extremes of each gate (0 V and −2 V) to determine the full-scale current and set a threshold (20% of full scale) that defines the hypersurface. The gate-voltage domain considered spans up to eight gate voltages, each within [0, −2 V], selected to avoid leakage currents. - Sampling stage (hypersurface search and modeling): In each iteration, select a random search direction u (unit vector) from the origin and scan along the ray until the current falls below threshold, defining an intersection with the hypersurface. Implement pruning: step back from the intersection by ±100 mV per gate, sweep each gate downward to check whether the hypersurface is encountered; if only one gate axis causes the intersection, constrain future searches by pruning non-informative axes. Build a probabilistic model of the hypersurface using measurements; the model is updated iteratively and fitted using flexible nonparametric regression (Gaussian processes are mentioned as a modeling choice). Weighting: assign a probability P_peak over the hypersurface indicating likelihood to observe Coulomb peaks based on prior observations. Candidate locations on the hypersurface are generated (e.g., via simulated Brownian motion collisions with the modeled surface) and sampled with probability proportional to P_peak. Subsequent scans begin near the modeled hypersurface (using g(u) = f − (m(u) − 2s)u) rather than the origin to improve efficiency, with direction reversal if starting below threshold. - Investigation stage (feature detection and scoring): At each selected hypersurface point, investigate nearby voltage space in the plane spanned by two preselected plunger gates (V3 and V7) that primarily shift the left and right dot potentials. Perform a 1D diagonal scan along V_e = (V3 + V7)/√3 with 128 mV length and 1 mV resolution to detect Coulomb peaks. If peaks are absent, abort investigation and return to sampling. If peaks are present, acquire a 2D current map in the (V_e, V_a) plane with V_a = (V3 − V7)/√3. Use a low-resolution scan (e.g., 16×16 or 20×20 pixels) over a square whose side is 3.5× the average Coulomb peak spacing from the diagonal scan (default 100 mV if fewer than three peaks). Compute a score via a predefined function engineered to identify transport features such as aligned, repeating peaks and honeycomb patterns expected for double quantum dots. If the score exceeds threshold, acquire a high-resolution map (e.g., 60×60 pixels). The presence of Coulomb peaks and scores are fed back to update P_peak on the hypersurface model. Peak detection is used to avoid excessive 2D mapping when features are unlikely. - Ablation configurations: Besides the Full decision algorithm (hypersurface sampling with weighting and pruning, peak detection, and score-function gating of high-resolution scans), reduced variants include Pure random (uniform sampling in full space with peak detection only), Uniform surface (hypersurface sampling without weighting/pruning), and Peak weighting (hypersurface sampling with weighting/pruning and peak detection but without score-function gating for high-res acquisition). Investigation parameters for ablations used low (20×20) and high (60×60) resolution settings. - Device variability analysis: Using the Uniform surface module without investigation, collect hypersurface point sets across runs/devices or before/after thermal cycling. Quantify variability by registering point sets via coherent point drift (affine transform with translation fixed to zero), yielding a matrix B (deviation from identity) whose diagonal elements reflect gate-capacitance scale changes and off-diagonals reflect cross-capacitance (shear) changes.

- The algorithm automatically tunes gate-defined double quantum dot devices in high-dimensional (up to 8D) gate-voltage spaces starting from full ranges, locating operational transport features while minimizing the number of current maps required. - Reported median tuning time under 10 minutes from the full gate-voltage ranges, surpassing the best human benchmark; and approximately 180× faster than an automated random search of parameter space (notably in ablation comparisons without peak detection, where Pure random would require a posterior estimate of ~680 h). - Human benchmarking: experienced humans require ~3 h to tune a similar device to exhibit double quantum dot features; multi-labeler Bayesian analysis estimated success time µ for Device 2 with median 2.8 h (80% credible interval 1.9–7.3 h) for a defined success criterion (acquiring a high-resolution map later confirmed by humans), indicating superhuman performance in that operational definition and context. - Grouped-gates strategy (reducing dimensionality by grouping electrodes with similar function) improved median µ to 0.6 h with 80% credible interval (0.4, 1.1) h, significantly reducing time versus ungrouped runs. - Probability of finding peaks, P(peaks), is markedly increased by the algorithm relative to Pure random, leading to more efficient identification of candidate double-dot regions. Across ablations, P(success|peaks) remains similar, while P(peaks) drives performance differences. - Ablation study shows: hypersurface sampling is crucial (Uniform surface vs Pure random); weighting and pruning further improve efficiency (Peak weighting vs Uniform surface); the score-function decision accelerates tuning by reducing unnecessary high-resolution scans (Full decision vs Peak weighting). - Device variability quantified: affine transformations derived from hypersurface point-set registration show that thermal cycling in Device 2 mainly induces uniform capacitance changes across gates (diagonal B), whereas variability between Devices 1 and 2 (similar architecture) exhibits nonuniform gate-capacitance changes and altered cross-capacitances (off-diagonal B), consistent with charge traps/defects and fabrication differences.

The findings demonstrate that combining minimal physics-based assumptions (features lie near a current-boundary hypersurface) with flexible probabilistic models and targeted measurements enables efficient, fully automatic tuning of semiconductor quantum devices. By focusing search on a modeled hypersurface, pruning ineffective axes, and using peak detection and a feature score to triage mapping, the algorithm substantially reduces measurement time relative to naive exploration and performs at or beyond expert human capability for the defined success criteria. The approach generalizes across devices with differing gate counts and is adaptable to other architectures and readout modalities because it imposes few structural assumptions on the hypersurface shape. Quantifying device variability via hypersurface registration provides a practical metric for changes due to thermal cycling and inter-device differences, offering insights into capacitance and cross-capacitance variations that can inform device design and control strategies. Overall, the method addresses a key bottleneck in scaling quantum dot arrays by automating coarse tuning and enabling robust operation despite device-to-device variability.

The paper introduces a machine learning algorithm that automatically tunes multi-gate quantum dot devices by efficiently navigating high-dimensional gate-voltage spaces using a modeled boundary hypersurface, pruning, and feature-driven investigation. It achieves rapid tuning, surpasses human benchmarks, and dramatically outperforms random exploration. An ablation study validates the contribution of each module, and a grouped-gates strategy further accelerates tuning. The framework additionally provides a quantitative method to assess device variability across thermal cycles and between devices. Future directions include extending to higher-dimensional devices and other platforms, integrating faster measurement techniques and alternative readouts (e.g., charge sensing, dispersive), optimizing score thresholds and decision policies, and leveraging device-aware grouping or adaptive dimensionality reduction to further reduce tuning times.

Evaluation relies on human labeling of current maps for confirmation, introducing subjectivity despite multi-labeler Bayesian aggregation. Experiments were conducted on two GaAs/AlGaAs devices with similar gate architectures, limiting generalizability pending broader validation across materials and designs. Performance depends on measurement settings (e.g., thresholds, scan resolutions) and assumes that transport features are sufficiently captured by current maps in the selected plunger-gate plane; alternative readouts may require additional optimization. Device issues such as leakage on specific gates necessitated excluding some electrodes, and thermal cycling introduces variability that can alter the hypersurface, potentially affecting reproducibility. Without peak detection, measurement times become prohibitive, indicating reliance on that module for practicality.