Gate controlled valley polarizer in bilayer graphene

The valley degree of freedom in graphene, originating from its hexagonal structure, is exploitable in electronic devices. Valley filters are particularly interesting for studying electronic transport with non-zero Berry curvature. Valley currents are not easily detected; typically, a non-local geometry and the inverse valley Hall effect are used. Gate-controlled chiral channels offer a robust and flexible approach. Theory predicts that sign reversal of Berry curvature in adjacent bilayer graphene (BLG) regions, achieved using dual-split gates, produces topological valley-polarized one-dimensional (1D) channels with quantized conductance 4e²/h in the ballistic limit. Previous gate-controlled polarizers had limited contrast due to disorder causing valley mixing and backscattering, requiring external magnetic fields to suppress backscattering. However, high magnetic fields limit applications. This work aims to improve gate-controlled valley polarizer performance at zero magnetic field using optimized geometry and stacking.

Several methods for creating valley currents exist, including circularly polarized light, magnetic control, and counter-propagating bulk currents. However, optical and magnetic control are not always feasible, and net bulk valley currents lack flexibility. Previous work on gate-controlled valley polarizers in bilayer graphene demonstrated good contrast only in the presence of a significant external magnetic field (8T). This magnetic field, however, drives the ungated regions into the quantum Hall regime, limiting the applicability of the valley-polarized electrons. Prior experiments using naturally occurring stacking boundaries or gate-controlled approaches showed limitations due to disorder and backscattering, necessitating the exploration of improved device fabrication techniques to enhance the performance of gate-controlled valley polarizers in zero magnetic field.

This study focused on optimizing the device geometry and fabrication process to improve the performance of a gate-controlled valley polarizer in bilayer graphene at zero magnetic field. Electrostatic simulations using finite element methods were employed to model the device and assess the impact of device asymmetries on charge inhomogeneity. The simulations considered the effects of gate spacing, dielectric thickness, and misalignment, aiming to minimize charge disorder. The fabrication process involved stacking hexagonal boron nitride (hBN), bilayer graphene (BLG), and hBN layers using a dry van der Waals method to reduce disorder. The bottom gates were patterned using few-layer graphene and oxygen plasma etching. Top gates were fabricated using electron-beam lithography (EBL), with careful attention to alignment and dimensional control. Electrical measurements were performed at 1.4 K using a four-probe configuration. The chiral nature of the 1D channels was verified using a valley analyzer configuration involving two gate pairs.

The optimized device geometry and fabrication method yielded significantly improved performance of the gate-controlled valley polarizer. Electrical measurements revealed a conductance difference of up to two orders of magnitude between the valley-polarized state and the gapped states. The valley-polarized state exhibited a conductance of nearly 4e²/h, consistent with the theoretical prediction of four quantized conduction channels. Measurements in a valley analyzer configuration confirmed the chiral nature of the 1D channels. Careful adjustment of top-gate spacing minimized induced charges in the split region, reducing gate-induced disorder. The on/off contrast between the valley-polarized state and the gapped state reached approximately 100, substantially higher than previously reported results. Analysis of the channel conductance, accounting for series resistance from ungated BLG and contact resistance, indicated a channel resistance close to the theoretical expectation for four ballistic channels, although a slight deviation was observed and attributed to potential inhomogeneities or parallel conduction paths. Experiments using a second gate pair as a valley analyzer confirmed the chiral nature of the 1D channels, further supporting the creation of a valley-polarized state.

The results demonstrate the successful creation and manipulation of electrically controlled valley-polarized 1D conduction channels in bilayer graphene at zero magnetic field. The significant improvement in performance compared to previous studies highlights the importance of optimized device geometry and fabrication techniques in minimizing disorder and enhancing valley polarization. The observed conductance close to 4e²/h in the valley-polarized state and the confirmation of chiral nature through valley analyzer measurements provide strong evidence for the successful realization of a robust gate-controlled valley polarizer. The observed slight deviation from ideal ballistic transport might be explained by remaining inhomogeneities or other forms of scattering. This achievement opens pathways to further investigate valleytronics at zero magnetic field and explore applications of valley-polarized electrons in various devices.

This work demonstrates a significant advancement in gate-controlled valleytronics by achieving high-performance valley polarization in bilayer graphene without external magnetic fields. Optimized device geometry and fabrication techniques were crucial for minimizing disorder and enhancing the on/off ratio. Future research could focus on further reducing disorder, exploring different gate geometries, and investigating the potential for more complex valleytronic devices and circuits.

While this study demonstrates significant improvements, certain limitations exist. The slight deviation from the expected conductance of 4e²/h in the valley-polarized state suggests some remaining inhomogeneities or scattering mechanisms. Further reduction in disorder and optimization of the device geometry might be necessary to achieve truly ballistic transport. Moreover, the study focused on a specific device geometry and fabrication method; investigating the scalability and generalizability of these results to other device architectures and fabrication techniques is important for future development.