A tactile sensor system with sensory neurons and a perceptual synaptic network based on semivolatile carbon nanotube transistors

The study addresses how to emulate human-like tactile perception using energy-efficient neuromorphic hardware. Traditional digital downscaling has reached limits for AI tasks, prompting interest in analog devices whose multilevel, low-energy, and often nonvolatile states can emulate synapses and neurons. Volatile analog behaviors have been used to mimic short-term synaptic plasticity and leaky integrate-and-fire neuronal integration, enabling temporal pattern classification. The authors identify a gap: implementing both neuronal (leaky integration) and synaptic (learning/recognition) functions using a single device type to simplify neuromorphic systems. They propose a biorealistic tactile sensor system in which a semivolatile CNT transistor operates in either volatile or nonvolatile mode depending on bias, thereby acting as both sensory neuron and synapse. A tactile sensor converts pressure to resistance, a voltage-controlled oscillator (VCO) converts resistance to spike frequency, a volatile-mode CNT transistor integrates spikes, and a nonvolatile CNT transistor array performs supervised perceptual learning to recognize temporal tactile patterns.

Prior work established analog devices for neuromorphic computing, including memristive crossbars for learning and recognition and device-level emulation of synapses and neurons. Volatile behaviors were used to emulate short-term plasticity (e.g., paired-pulse facilitation) and leaky integrate-and-fire neurons capable of integrating temporally correlated inputs. Some devices exhibit switchable volatile/nonvolatile operation (referred to as semivolatile or second-order memristors), previously explored mainly to model psychological transitions from short-term to long-term memory. However, leveraging a single semivolatile device to simultaneously implement neuronal and synaptic functions across an entire neuromorphic tactile system had not been fully explored. This work builds on these foundations by using a semivolatile CNT transistor for both functions and integrating it with a tactile sensor and VCO for temporal pattern recognition.

System architecture: The tactile system comprises (i) a flexible tactile sensor that transduces pressure into resistance changes, (ii) a VCO that converts resistance into spike frequency, (iii) a CNT transistor operating in volatile mode as a sensory neuron for leaky temporal integration, and (iv) a CNT transistor array operating in nonvolatile mode as a synaptic network for supervised learning and recognition. Tactile sensor fabrication: A PDMS substrate (1 mm) was prepared by mixing Sylgard 184A prepolymer and curing agent at 10:1 (w/w), oxygen plasma cleaning, and functionalization with 0.1% w/v poly-L-lysine. A 99% metallic CNT network was spray-coated from 0.01 mg/mL solution on a 100 °C hot plate, then rinsed with isopropanol and DI water. Cu electrodes were attached using silver paste. A top PDMS layer was cast to form a sandwich structure. Final anneal at 100 °C for 1 h. Semivolatile CNT transistor array fabrication: Devices were built on p-doped Si with 50 nm thermal SiO2. A local back-gate (Ti 20 nm) was formed by e-beam evaporation and lift-off. Gate dielectrics were deposited by ALD: Al2O3 (40 nm) followed by SiO2 (10 nm). The SiO2 surface was functionalized with poly-L-lysine (0.1 g/mL, 20 min). A 99% semiconducting CNT network channel was formed by immersing the chip in 0.01 mg/mL solution at 100 °C for 8 min. Source/drain electrodes (Ti 2 nm/Pd 30 nm) were thermally evaporated and patterned via lift-off. Unwanted CNTs were removed by photolithography and oxygen plasma etch to isolate devices. For crossbar arrays, Cu (80 nm) interconnects and SiO2 (150 nm) ILD were deposited and patterned. Device operation principle and biasing: CNT transistors exhibit ID–VG hysteresis due to hole trapping/detrapping at interface traps (fast tunneling) and surface traps (slow lateral diffusion). Preconditioning used −6 V DC on the gate for 1 s to fill traps. For transient tests, a read level Vlow = −3 V (undisturbed) and 5 µs pulse widths were used to avoid cumulative effects. A single gate pulse with amplitude Vhigh ejects trapped holes; if Vhigh ≥ ~2.5 V, both interface and surface traps are emptied resulting in a nonvolatile increase in ID (ΔGLT > 0). If Vhigh < ~2.5 V, mainly interface traps are affected and ID shows a temporary increase (ΔGST > 0) followed by decay (volatile mode). Metrics: ΔGST = (Ipeak − Istart)/Istart and ΔGLT = (Iend − Istart)/Istart. Volatile (neuronal) operation: Trains of presynaptic spikes Vpre with frequency fpre were applied. Due to leaky integration, higher fpre yields larger cumulative enhancement in ID and higher Ipeak; lower fpre allows decay between pulses, reducing Ipeak. A compact circuit model using two RC branches captured fast (tunneling) and slow (diffusion) dynamics and matched measured transients. VCO design and sensor-to-spike conversion: The tactile sensor’s pressure-induced resistance change ΔRsensor (≈2.5–10 MΩ) was fed to a digital VCO implemented on a PCB. The VCO produced Vpre pulses with frequency increasing monotonically with pressure (higher pressure → lower Rsensor → higher fpre). The Rsensor–fpre transfer was quantitatively characterized and matched circuit simulations. Pattern acquisition and classification task: A 10×10 CNT transistor array was fabricated; one selected device operated in volatile mode as the neuronal element; a 10×4 subset operated in nonvolatile mode as the synaptic network. As a proof-of-concept, two-position tactile patterns in one row (convex=“1”, flat=“0”) produced four classes: 00, 01, 10, 11. The tactile sensor, attached to a finger, was moved across the patterns left-to-right, completing a touch sequence in ≤1 s. Pressure events over “1” generated transient ID increases; “0” produced no change. The neuronal output ID(t) was sampled post-touch over 1 s at 0.1 s intervals to form an input vector Ui normalized by Iref (0 ≤ Ui ≤ 1). These samples were then fed to the synaptic CNT array (operated in nonvolatile mode) for supervised learning; boundary vectors Wj were defined for class separation (details truncated in provided text).

- Switchable semivolatile operation: The CNT transistor exhibits two modes controlled by gate pulse amplitude. For Vhigh < ~2.5 V, behavior is volatile (ΔGLT ≈ 0) with transient ID enhancement and decay; for Vhigh ≥ ~2.5 V, nonvolatile conductance change appears (ΔGLT > 0), enabling synaptic weight storage. - Frequency-dependent leaky integration: Under volatile operation, ΔGST increases with presynaptic frequency fpre, enabling encoding of pressure intensity via spike frequency and neuronal integration, consistent with leaky integrate-and-fire behavior. - Sensor-to-spike conversion: The tactile sensor shows pressure-dependent resistance changes (~2.5–10 MΩ). A VCO converts Rsensor to Vpre with fpre increasing with pressure; measured Rsensor–fpre relation matches circuit simulation. - Temporal pattern discrimination: The neuronal device output ID(t) distinguishes patterns 00, 01, 10, 11. The “11” pattern yields the largest response due to two successive stimuli. Despite both having a single convex feature, “01” produces a higher ID at sampling than “10” due to decay timing, demonstrating sensitivity to temporal order. - Circuit-level validation: A compact RC-based model accurately reproduces transient device responses and, when combined with the VCO model, quantitatively predicts system behavior, supporting product-level feasibility. - Learning capability: The system is designed for supervised learning in a synaptic CNT array, with recognition accuracy that improves through iterative learning (as stated in the abstract), demonstrating perceptual learning of tactile features.

The work demonstrates that a single semivolatile CNT transistor type can fulfill both neuronal (volatile, leaky integration) and synaptic (nonvolatile, memory) roles by adjusting bias conditions. This addresses a key challenge in neuromorphic hardware: reducing device heterogeneity and fabrication complexity while preserving biorealistic processing. By encoding pressure as spike frequency via a VCO and leveraging the frequency-dependent integration of the volatile device, the system extracts temporal features of tactile inputs, similar to biological sensory pathways. The nonvolatile array then supports perceptual learning and recognition, showing that temporal order in tactile patterns is discriminable. The accurate circuit model spanning device physics (tunneling/diffusion dynamics) to system-level VCO-sensory interfaces enables quantitative analysis and design, indicating potential scalability and practical integration. These findings advance neuromorphic tactile sensing and suggest routes for energy-efficient, compact sensory systems applicable to robotics and prosthetics.

The authors present a biorealistic tactile sensing system wherein both sensory neurons and a perceptual synaptic network are implemented using semivolatile CNT transistors. By bias-controlled switching between volatile and nonvolatile modes, the same device type performs leaky integration of spike trains and long-term weight storage. A tactile sensor plus a digital VCO convert pressure to spike frequency; the neuronal device extracts temporal features; and a nonvolatile CNT array learns to recognize simple temporal patterns. A compact circuit model accurately reproduces device and system responses, underscoring quantitative and product-level feasibility. Future work could scale to larger arrays and richer tactile scenes, integrate on-chip VCO and sensing elements, develop fully on-chip learning, quantify recognition accuracy and energy, and explore robust, real-world robotic and prosthetic applications.

The provided text does not report detailed quantitative recognition accuracy, energy consumption, or robustness metrics. The classification task involves simple two-position patterns and a limited array subset (10×4 synaptic devices), so generalization to complex tactile scenes is not demonstrated here. Real-time on-chip integration details (e.g., integrated VCO and controller) and long-term stability, variability, and endurance data are not provided in the excerpt.