A system-on-chip microwave photonic processor solves dynamic RF interference in real time with picosecond latency

The paper addresses dynamic radio-frequency (RF) interference that threatens critical applications such as radar altimeters operating near 5G cellular bands. As wireless systems expand in frequency and adopt spatial multiplexing, interference becomes more pervasive, and low-latency RF front-ends are increasingly vital for safety-critical domains (transportation, healthcare, military). Future wireless generations will further tighten latency requirements due to higher data rates, carrier frequencies, and user mobility. Movement of transceivers leads to time-varying mixing ratios between the signal-of-interest (SOI) and interferers, necessitating real-time adaptability in receivers. Photonic integrated circuits (PICs) can process broadband information by upconverting RF to optical frequencies, offering ultra-low latency analogue processing compared with bandwidth-limited analogue RF components and clock-limited digital electronics. Prior PIC demonstrations have achieved tens of nanoseconds latency even with off-chip conversions, and fully integrated on-chip modulators and photodetectors promise even lower latency. However, realising a compact microwave photonic system-on-chip has been constrained by design, control, and packaging complexities; most prior systems lacked co-packaged electronics for real-time operation, relied on pre-trained static weights, and used bulky lab equipment for digitisation and control, leading to high size, weight and power (SWaP) and non-real-time operation. The authors propose blind source separation (BSS) as an interference suppression mechanism that avoids prior knowledge of sources, leveraging statistical non-Gaussianity to recover original signals. They implement BSS in silicon photonics using microring resonator (MRR) weight banks and co-packaged FPGA-based control and learning to deliver real-time, low-latency interference mitigation suitable for mobile scenarios.

Conventional interference mitigation often depends on prior knowledge: spectral filtering separates by centre frequency; adaptive beamforming suppresses by direction of arrival; cognitive radio coordinates spectrum usage. In practice, obtaining such knowledge is difficult due to independent operators, privacy constraints, random/bursty traffic, and delays in acquiring channel state information and training for prediction. Blind source separation (BSS) avoids these issues by recovering sources using statistical properties (e.g., kurtosis of outputs), enabling compatibility with dense, mobile RF environments. Photonic hardware can realise linear demixing for BSS using MRR weight banks, meshes of Mach–Zehnder modulators (MZMs), and phase-change material (PCM) crossbar arrays, which offer high energy efficiency and instantaneous bandwidth, eliminating frequency switching. Silicon photonics supports chip-scale integration and CMOS compatibility. Control precision comparable to digital resolution can be achieved via techniques like dithering. Prior PIC demonstrations often had larger latencies and lacked integrated, real-time peripheral electronics, relying on oscilloscopes, computers, and bench-top sources, resulting in slow, offline control and poor SWaP, limiting real-world deployment.

System architecture: A fully integrated silicon photonic signal pathway performs linear demixing in the analogue domain on-chip, co-packaged with an FPGA-based digital peripheral for statistical analysis and control. Two PN-type microring resonator (MRR) modulators encode two RF inputs onto two lasers (Pure-Photonics PPCL500) tuned to the MRR resonances. The PN junctions are slightly reverse-biased (~0.55 V) and provide broadband electro-optic modulation via free-carrier dispersion. Measured modulator 3-dB bandwidth is ~5.4 GHz with usable modulation efficiency (<10 dB roll-off) up to ~9.7 GHz. The modulated optical carriers are split and processed by two MRR weight banks (supporting wavelength-division multiplexing for scalability), which thermally tune weights; transitioning from most negative to most positive weight requires <2.5 mA, ~<4.5 mW per MRR, totaling ~18 mW for a 2×2 demixing operation. Optical outputs at each weight bank’s drop and thru ports feed a balanced photodetector (BPD; responsivity ~1 A/W, bias ~1.1 V) that performs differential detection to convert to electrical signals. Each BPD output is amplified by a transimpedance amplifier (TIA, Analog Devices HMC7590), providing duplicate outputs: one to the FPGA for analysis and one as system RF output. Two parallel links enable simultaneous recovery of both original signals. The integrated optical path length is ~1.6 mm with refractive index ~2.44, giving ~15 ps light-propagation latency; overall end-to-end latency (including modulator RC, TIA delay, and board traces) is <200 ps. Measured link loss is <15 dB up to ~5.8 GHz. Digital peripheral and learning: A Xilinx RFSoC4x2 FPGA integrates ADCs, programmable logic (PL), and ARM processing system (PS). ADC sampling is 4.915 GSPS with frames of 2^15 samples. The PL computes kurtosis in a pipelined manner at the acquisition rate. The PS runs a Nelder–Mead (NM) optimisation to adjust demixing weights to maximise non-Gaussianity (kurtosis κ = μ4/σ^4) of outputs, using a simplex of n+1 weight vectors for n inputs (2×2 case). Communication to the MRR driver uses a high-speed SPI. Timing per update cycle: ~0.3 ms (communication), ~2 ms (statistical analysis), ~1 ms (MRR thermal tuning), enabling a 305 Hz weight update rate. Typical convergence from random initial weights requires ~10 iterations (~33 ms). Accurate kurtosis estimation can be achieved with sub-Nyquist sampling, reducing power; the complete system power is <10 W. Packaging and SWaP: The photonic processor is packaged on a compact high-frequency PCB with impedance-controlled traces; a second PCB houses multi-channel DACs for MRR tuning and biasing. A reflective fibre array is epoxy-coupled to grating couplers for stable, low-profile optical I/O. The assembled system measures ~40 mm × 30 mm, suitable for handheld/mobile deployment. Benchmarking: A digital electronic baseline at 100 MHz clock with 16-bit data and 9-bit weights requires ~240 ns for the linear demixing multiplication alone (excluding ADC/DAC), highlighting the >1000× latency advantage of the photonic approach. Energy comparison indicates ~18 mW for photonic 2×2 weighting vs ~172 mW for an electrical processor (0.43 pJ per weighting at 100 GS/s). Experiments: The system is validated in two dynamic interference emulation scenarios (mobile communications and radar altimeters). The receiver obtains two mixtures (e.g., via orthogonal polarisations in a 2×2 MIMO antenna) with time-varying mixing ratios due to transmitter/receiver motion; the photonic BSS demixes in real time with continuous FPGA-driven weight updates.

- Ultra-low latency: On-chip photonic demixing latency <15 ps (propagation), with overall RF-in to RF-out latency <200 ps including electronics and interconnects. A comparable digital system requires ~240 ns for the multiply operation alone at 100 MHz (excluding conversion latencies), indicating >1000× speedup. - Real-time adaptive operation: FPGA-co-packaged control achieves a 305 Hz demixing weight update rate; typical convergence in ~10 iterations (~33 ms) from random initial weights, enabling tracking of time-varying mixing. - Bandwidth and link performance: MRR modulator 3-dB bandwidth ~5.4 GHz; usable modulation to ~9.7 GHz; overall link loss <15 dB up to ~5.8 GHz. - Energy and SWaP: Photonic 2×2 weighting consumes ~18 mW (<4.5 mW per MRR), versus ~172 mW estimated for an electrical processor at 0.43 pJ/weighting and 100 GS/s. Complete system power <10 W. The packaged module is compact (≈40 mm × 30 mm) and suitable for mobile use. - Demonstrated interference suppression: In emulated mobile communications and radar altimeter scenarios, the system maintains SNRs >15 dB and achieves error-free transmission over 800 bits while demixing in real time under dynamic mixing conditions. - Integrated pathway and packaging: Fully integrated optical path (modulators → MRR weight banks → BPDs) with stable fibre coupling and impedance-engineered PCB; co-packaged FPGA with ADC/PL/PS enables high-throughput kurtosis computation and rapid weight control (SPI).

The study targets dynamic RF interference where mixing ratios between the SOI and interferers vary rapidly due to mobility. By implementing BSS directly in the analogue photonic domain with a fully integrated signal path, the system achieves picosecond-scale processing latency, which is orders of magnitude faster than digital approaches and critical for safety-of-life applications (e.g., aircraft radar altimeters, autonomous systems). The co-packaged FPGA enables online learning through kurtosis-based optimisation (Nelder–Mead), updating weights at 305 Hz to track time-varying channels. This combination addresses both the bandwidth/latency bottlenecks of DSP and the need for real-time adaptability. The demonstrated preservation of SNR (>15 dB) and error-free transmission in representative scenarios indicates that photonic BSS can robustly recover SOIs amidst dynamic interference with favourable SWaP, pointing to practical field deployment potential. The approach also leverages the scalability of WDM and the analogue precision of photonics, aligning with future wireless trends toward higher carrier frequencies and denser spectral usage.

The work demonstrates a palm-sized, system-on-chip silicon photonic processor that performs blind source separation with sub-15-ps intrinsic latency and <200-ps end-to-end latency, co-packaged with FPGA-based online learning for 305 Hz weight updates. It achieves real-time suppression of dynamic RF interference and successfully recovers signals-of-interest in emulated radar altimeter and mobile communication scenarios, maintaining high SNR and error-free transmission over tested sequences. The results establish the real-time adaptability of integrated silicon photonics with on-chip signal pathways and co-integrated electronics, offering a path beyond the latency and power limits of conventional DSP. Potential future directions include scaling to higher-dimensional MIMO using WDM and additional weight banks, increasing update rates, expanding bandwidth, further integration with CMOS control, and validating performance in more complex, real-world RF environments.

- Demonstrations focus on a 2×2 case (one SOI and one interferer), representing a modest computational scale; performance for larger numbers of sources/mixtures is not reported. - Weight updates rely on thermal tuning (~1 ms per update step) and converge in ~10 iterations (~33 ms); while sufficient for demonstrated dynamics, faster channel variations may challenge tracking. - Reported error-free performance is over 800 bits in the test scenarios; longer transmissions and broader protocol evaluations are not detailed in the provided text. - Overall link loss (<15 dB to ~5.8 GHz) and modulator bandwidth (~5.4 GHz 3-dB) may constrain certain higher-frequency applications unless further optimised. - Comparison to digital baselines excludes ADC/DAC conversion latencies and system-level overheads for both approaches; a full system comparison is not provided.