A FinFET with one atomic layer channel

The study addresses the continued scaling of field-effect transistors (FETs) dictated by Moore’s law and the limitations faced by conventional planar FETs at sub-10 nm channel widths due to quantum confinement effects. FinFET architectures improve electrostatic control by wrapping the channel with the gate, but the fin width (Wfin) has plateaued at a few nanometers because of lithography limits. Prior work explored low-dimensional materials, including 2D MoS2 with sub-1 nm gate lengths using CNT gates, CNT channels with graphene contacts, and few-layer TMDs and CNT films in FinFETs. While 2D semiconductors mitigate short-channel effects, their planar use does not significantly reduce footprint. The key research goal is to realize a vertically free-standing monolayer (ML) 2D van der Waals channel as a fin to reach the single-atom fin-width limit while preserving large fin height, overcoming lithography constraints. The authors propose and demonstrate a universal template-growth method to vertically isolate ML 2D crystals and fabricate ML-FinFETs.

• Scaling limitations: FinFETs fabricated top-down are constrained by lithography, with narrowest line widths ~6 nm, limiting further Wfin reduction.
• Alternative device structures: Demonstrations include 2D MoS2 planar FETs with CNT gates achieving sub-1 nm gate length; CNT-based channels with graphene contacts; few-layer MoS2 and CNT films serving as channels in novel FinFETs.
• 2D materials advantages and gaps: 2D semiconductors are less prone to short-channel effects but planar implementations occupy comparable chip area to Si technologies, limiting scaling benefits.
• Targeted innovation: Vertically oriented monolayer 2D crystals would achieve single-atom fin width while maintaining fin height, but had not been experimentally realized due to challenges in growing vertically free-standing 2D nanoflakes.

• Template growth on SOI steps: Fabricate ~300 nm vertical step edges in arrays on SOI wafers via photolithography and ICP-RIE. Coat sidewalls with ~10 nm HfO2 using ALD, followed by anisotropic dry etching to remove planar HfO2 (plane-removing process), leaving HfO2 on sidewalls to protect/support subsequent 2D flakes.
• Wet-spray CVD for monolayer 2D growth: Optimize a wet spray CVD process to conformally grow monolayer TMDs (e.g., MoS2, WS2) and thin films (e.g., CNT films) over the step-edge templates, achieving vertical coverage of the step. ML nature verified by supplementary characterizations.
• Device fabrication workflow: 1) Prepare sharp 300 nm edge with HfO2-coated sidewall. 2) Grow ML TMD via wet-spray CVD over the step. 3) Deposit HfO2 coating and pattern/evaporate source–drain (S–D) electrodes with optimized evaporation angle/thickness for improved contact. 4) Plane-removing process to etch away planar parts of the ML TMD, retaining only the material on the vertical sidewall supported by HfO2. 5) Wet etch to remove the 300 nm Si step, forming a vertical HfO2/TMD/HfO2 sandwich clamped by S–D electrodes. 6) Deposit gate dielectric (HfO2 by ALD) and form gate electrodes via metal deposition or CNT-film deposition, yielding a monolayer FinFET (ML-FinFET) with ~0.6–0.65 nm fin width.
• Variants: ML-Fin can be ML MoS2, ML WS2, or CNT thin films. Gate electrodes realized with metals or CNT films.
• Planar device benchmarking: Fabricated planar MoS2, WS2, and semiconducting CNT film FETs for comparison; room-temperature electron mobility ~10 cm2 V−1 s−1 in MoS2 planar devices.
• Experimental conditions and tools: Details provided for wet spray CVD precursor prep and growth (e.g., Na2MoO4/Na2WO4 solutions, S vaporization, 850 °C growth), CNT deposition protocols (semiconducting and metallic), nanofabrication equipment (ALD HfO2 at 150 °C; RIE), and electrical measurements (Agilent B1500A, probe station).
• Finite element simulations: COMSOL Multiphysics semiconductor module with Maxwell’s equations and Boltzmann transport, Neumann boundary conditions. 3D FinFET model with gate wrapping three sides; gate–source/drain gap 4 nm. Source/drain heavily n-doped (1e20 cm−3), channel slightly n-doped (1e15 cm−3) for convergence. ML MoS2 thickness set to 0.65 nm; gate lengths simulated at 200, 100, 50, and 4 nm; HfO2 dielectric thickness 2 or 20 nm. SRH recombination included. Screening length estimated by λ = sqrt(εSiO2/εHfO2)·WSiO2·WHfO2.

• Fabrication achievement: Demonstrated vertical, free-standing monolayer (ML) 2D crystal fins integrated into FinFETs using a universal bottom-up template-growth method, reaching a physical fin width limit of ~0.6–0.65 nm (one atomic layer).
• Device performance (experiments):
  • On/off current ratios across devices span ~10^2 to ~10^7; best devices reach ~10^7.
  • Best subthreshold swing (SS): ~300 mV/dec.
  • Output characteristics exhibit linear I–V behavior in representative ML-FinFETs.
  • Extracted field-effect mobilities in ML-FinFETs: ~1–6 cm2 V−1 s−1 (room temperature).
  • Planar MoS2 FETs from the same growth show mobilities ~10 cm2 V−1 s−1; WS2 planar FETs and semiconducting CNT film FETs show similar trends.
• Process insights:
  • HfO2 sidewall coating is critical for retaining the vertical ML fin; absence of this support fails to yield the fin structure.
  • Both metal and CNT-film gates implemented with comparable behavior.
• Simulation results (idealized structures):
  • For a 4 nm gate length ML-FinFET with 0.65 nm fin and 2 nm HfO2: screening length λ ≈ 0.26 nm; simulated on/off ratio ~10^11; DIBL ≈ 5 mV/V; strong gate control with suppressed short-channel effects at VDS = 0.1–1.5 V.
  • Performance trends versus gate length and dielectric thickness indicate potential for significant improvement with optimized materials and geometry.
• Integration potential: Fabricated ML-Fin arrays with 300 nm fin height and minimum pitch of 50 nm, suggesting suitability for high-density integration.

The work directly addresses the challenge of further scaling FinFETs beyond lithography limits by introducing a bottom-up method to realize a monolayer-thick fin, reducing Wfin to the one-atom limit while maintaining substantial fin height. The achieved on/off ratios up to ~10^7 and functional devices with both metal and CNT-film gates validate the feasibility of the architecture. Although the experimental SS (~300 mV/dec) and mobilities (1–6 cm2 V−1 s−1) are modest, they are primarily limited by material quality from the wet-spray growth, not by the device geometry. COMSOL simulations of ideal ML-FinFETs with 4 nm gate length predict excellent electrostatic control (λ ~0.26 nm, DIBL ~5 mV/V) and very high on/off ratios (~10^11), indicating that the ML fin architecture can overcome short-channel effects more effectively than conventional Si or Si/Ge GAA devices when paired with optimized dielectrics and contacts. The demonstration of ML-Fin arrays with 50 nm pitch highlights the potential for dense integration in future low-power nanoelectronics.

This study introduces a universal bottom-up template-growth process to fabricate FinFETs featuring a single atomic layer fin (~0.6–0.65 nm), effectively pushing the fin-width (Wmin) to its physical limit. The approach is compatible with multiple 2D materials (MoS2, WS2) and gate types (metal, CNT-film). Experimentally, devices exhibit on/off ratios up to ~10^7 and a best SS of ~300 mV/dec, while simulations forecast superior short-channel control and high on/off ratios for optimized, short-gate devices. The results suggest a promising pathway toward next-generation, highly integrated, low-power nanoelectronics. Future work should focus on improving 2D material quality to enhance mobility and SS, optimizing dielectric interfaces and contacts, and scaling gate lengths while leveraging fin arrays for circuit-level integration.

• Material quality: The wet-spray CVD growth introduces defects and scattering centers, leading to relatively low carrier mobilities (1–6 cm2 V−1 s−1 in ML-FinFETs) and suboptimal SS (~300 mV/dec).
• Process dependency: The fin structure critically depends on HfO2 sidewall support; without it, the fin cannot be retained, indicating limited process margin.
• Performance gap to simulations: Experimental devices do not yet meet the simulated ideal performance, indicating the need for further optimization of growth, dielectric thickness/quality, and contact engineering.
• Characterization scope: The work focuses on DC characteristics; high-frequency, variability, and long-term reliability assessments are not reported.