27.09%-efficiency silicon heterojunction back contact solar cell and going beyond

The study addresses how to overcome recombination and transport losses in crystalline-silicon heterojunction back contact (HBC) solar cells to push efficiency beyond current records. Interdigitated back-contact (IBC) architectures eliminate front-side electrode shading and allow independent rear-side contact design, but introduce challenges including increased polarity boundaries, process-induced contamination, boundary recombination, and electrical shading. Prior advances in wafer-based c-Si technologies and passivating contacts (e.g., TOPCon, SHJ, POLO-IBC) have approached high Jsc and normalized electrical performance, yet integrating optimal passivation, low contact resistivity, and minimized current density loss within a single HBC device remains difficult. This work aims to fabricate large-area HBC solar cells via laser patterning, quantify recombination and resistive losses, and provide design strategies to mitigate boundary recombination and electrical shading to achieve ≥27% efficiency.

Previous record devices include Kaneka’s HBC cells achieving 26.7% efficiency with Jsc ≈ 42.5 mA·cm−2 and ISFH’s POLO-IBC cell at 26.1% using laser patterning. LONGI recently announced 27.30% efficiency for HBC. TOPCon cells (n- and p-type) reached 25.8% and 26.0% efficiencies with Jsc up to 42.87 mA·cm−2. While back-contact structures enhance optics, they are more susceptible than front-back contact (FBC) cells to process-induced recombination and electrical shading. Literature identifies key trade-offs among contact resistivity, passivation, and current collection, as well as the role of front/rear optical management, pn-junction recombination in IBC layouts, and effects of TCO properties. These works motivate careful management of polarity boundaries, gap designs, and contact stacks to reduce J02 and resistive losses, and to optimize optical performance.

- Device fabrication: Large-area n-type Czochralski Si wafers (M6, ~274.3 cm²) were processed using a laser-patterned HBC flow. Major steps: rear surface polishing and front texturing; sequential CVD of rear passivating layers (i-a-Si:H/n-a-Si:H/SiNx/i-a-Si:H); laser ablation to define HSC and ESC regions; wet etches (HF, KOH) for layer removal and surface preparation; deposition of i-a-Si:H/p-a-Si:H for HSC; subsequent laser patterning for ESC; HF to remove SiNx and laser-oxide; front-side i-a-Si:H/SiNx/SiOx ARC deposition; PVD ITO (SnO2:In2O3) TCO on both polarities; UV laser to open gap and remove TCO/stack for isolation; screen-printed Ag metallization and curing; light soaking (30 suns, 200 °C, 90 s). Final wafer thickness ~175 μm. - Monitoring samples: (1) Lifetime monitoring wafer partitioned into HSC, ESC, gap, and HSC+gap regions (taped to isolate regions before TCO) underwent same flow; (2) Dark I-V monitoring wafer with periodic HSC/gap on one side and full ESC on the other; TCO deposited both sides; Ag electrodes masked for sub-patterns. - Characterization: Certified light I-V (ISFH) for total and designated areas; EQE and reflectance; Suns-Voc and pseudo I-V; lifetime (Sinton WCT-120 MX); dark I-V (Keithley 4200A-SCS) with four-probe; transfer length method (TLM) to extract contact resistivity for HSC (on p-c-Si) and ESC (on n-c-Si); FTIR for a-Si:H microstructure; temperature-dependent conductivity for activation energies; LBIC with 532 nm, 20 μm spot. - Modeling and analysis: Simplified recombination model to extract J01, J02 and Rs from Suns-Voc and I-V; lifetime fitting model decomposing τeff into Auger, SRH, J01- and J02-related components; decomposition of dark I-V into HSC, gap, and boundary recombination with linear fitting vs perimeter/area to separate boundary contribution; calculation of metal resistive losses from busbar/finger networks; Quokka 3 3D simulations of unit cell for IQE and current flow; analytical estimation of Jrec vs transport length and effective lifetime to quantify electrical shading; derivation of optimal coverage area ratio between ESC and HSC based on their contact resistivity ratio to minimize Rs.

- Performance: Achieved certified 27.09% efficiency on designated illumination area (243.0 cm²) with Voc = 0.743 V, Jsc = 42.6 mA·cm−2, FF = 85.60%. On total area (274.3 cm²), achieved 26.74% with Voc = 0.745 V, Jsc = 42.1 mA·cm−2, FF = 85.29%, pFF = 86.9%. - Recombination parameters: Extracted J01 ≈ 1.1 fA·cm−2 (benefiting Voc ≈ 745 mV). Achieved low J02 ≈ 0.6 nA·cm−2 via built-in field engineering and polarity boundary control. Lifetime mapping showed ESC and gap regions with high effective lifetimes (~5000 μs at Δn = 5×10^15 cm−3), whereas HSC and HSC+gap were lower, indicating recombination concentrated in HSC and especially at HSC/gap polarity boundaries (J02 in HSC+gap ≈ 3.2 nA·cm−2, ~6× HSC alone). - Boundary recombination: Dark I-V on patterned test structures and linear fitting of J02 vs perimeter/area isolated strong polarity boundary recombination. An alkaline additive during wet etch reduced boundary roughness/concavities and lowered boundary-related J02. - Series resistance and contacts: Total Rs at MPP ≈ 0.34 Ω·cm² (higher than comparison cells with 0.22 and 0.20 Ω·cm²). TLM contact resistivity: HSC ≈ 51.3 mΩ·cm², ESC ≈ 46.1 mΩ·cm². Rs dominated by HSC/ESC stacks due to doped a-Si:H transport. Analytical/simulation maps show HBC Rs more sensitive to contact resistivity than FBC and provide an equation for optimal ESC coverage ratio based on Pc(HSC)/Pc(ESC). Microstructural tuning (narrowed i-a-Si:H bandgap at p/i interface; lower activation energy at p-a-Si:H/TCO) reduced contact resistivity near interfaces. - Jsc loss analysis: Decomposed current density losses showed Jfront ≈ 0.59 mA·cm−2, Jrear ≈ 0.69 mA·cm−2, and electrical shading Jshade ≈ 0.50 mA·cm−2 for the full-area HBC. Electrical shading primarily arises from longer minority-carrier transport across ESC/gap toward HSC and significant wafer edge recombination; LBIC revealed edge regions as major recombination channels once local electrical shading is mitigated. Designated-area testing (excluding edges) yielded higher Jsc (42.6 vs 42.1 mA·cm−2). - Analytical tool: Provided a compact relation linking Jrec to transport length and effective minority lifetime to rapidly estimate electrical shading and IQE for different HBC geometries and material qualities. - Outlook: Replacing doped a-Si:H with doped nanocrystalline Si in HSC/ESC stacks and hybrid contact stacks can reduce Rs below 0.12 Ω·cm², enhance FF to ~86.5%, and, together with improved front ARC/rear reflector and edge passivation, raise Jsc to ~42.8 mA·cm−2 and achieve PCE up to ~27.7%.

The work quantitatively identifies and mitigates the dominant recombination pathways limiting HBC cells: (1) surface/junction recombination in the HSC region and (2) severe recombination at polarity boundaries between HSC and gap. By refining the built-in field in HSC, controlling boundary morphology during wet processing (additive-assisted etching), and ensuring clean, well-passivated interfaces, J02 is suppressed to ~0.6 nA·cm−2, enabling high pFF. Resistive losses are traced primarily to contact resistivity of doped a-Si:H-based HSC/ESC stacks; sensitivity analysis and an optimization formula demonstrate that tailoring the coverage ratio of ESC to HSC to match their contact resistivity ratio can minimize Rs. Optical and transport analyses reveal that, beyond eliminating front electrode shading, HBC devices are susceptible to electrical shading due to long lateral transport in ESC/gap and to wafer-edge recombination that competes for carriers near edges. Simulations and LBIC confirm that once local shading is reduced, edge recombination becomes the principal channel of Jsc loss. These insights guide material (nanocrystalline contacts, hybrid stacks), structural (coverage optimization, minimal gap), and process (boundary smoothing, edge passivation, improved ARC and rear reflector) improvements that can jointly deliver further gains, making ~27.7% efficiency plausible.

This study demonstrates a laser-patterned large-area silicon heterojunction back-contact solar cell with certified 27.09% efficiency, achieving low J01 (~1.1 fA·cm−2), reduced J02 (~0.6 nA·cm−2), and high pFF, while diagnosing Rs and Jsc losses in detail. It establishes that recombination in the HSC and at polarity boundaries dominates J02, and that electrical shading and wafer-edge recombination are principal contributors to Jsc loss in HBC devices. An optimization framework links contact resistivity, series resistance, and contact coverage ratios, and a compact analytical model expedites evaluation of electrical shading. Future work should focus on adopting nanocrystalline passivating contacts or hybrid stacks to cut Rs (<0.12 Ω·cm²), managing polarity boundary morphology, implementing robust edge passivation, and refining front ARC and rear reflector designs. These strategies can collectively elevate normalized electrical performance and Jsc to realize HBC efficiencies around 27.7%.

- Series resistance remains higher than best-in-class devices due to doped a-Si:H transport in contact stacks; full optimization (e.g., nanocrystalline contacts) was not implemented. - Electrical shading and wafer-edge recombination still reduce Jsc in full-area measurements; designated-area results indicate potential gains if edge effects are suppressed. - Polarity boundary morphology from wet etching can induce concavities and TCO intrusion, elevating boundary recombination; although additives help, boundary control remains process-sensitive. - Gap-region recombination is negligible for the presented stack but may vary with alternative structures/materials and processing. - Some analytical expressions are simplified (e.g., effective lifetime assumptions, built-in field modeling) and may not capture all microstructural complexities at boundaries.