Weighted spin torque nano-oscillator system for neuromorphic computing

The work addresses limitations of von Neumann computing (notably power consumption) by proposing neuromorphic architectures that combine closely located processing and memory. The research question is whether a single multifunctional magnetic tunnel junction (MTJ) stack can implement a compact, CMOS-compatible neuromorphic building block that integrates non-volatile synapses and a nonlinear neuron with sufficient output power. The authors propose a weighted spin torque nano-oscillator (WSTNO) circuit that integrates MTJ-based non-volatile memories (MRAMs) as synaptic weights and a vortex spin torque nano-oscillator (STNO) as the neuron, all fabricated from one MTJ stack by varying lateral dimensions. They aim to demonstrate weighted summation with non-volatile weights and a nonlinear output suitable for neuromorphic inference with minimal footprint and energy.

The paper situates WSTNOs within neuromorphic hardware developments using memristors, photonics, spin Hall oscillators, and MTJs. Prior MTJ-based neuron implementations span rectifiers and linear/vortex STNOs with varying footprints and power: MTJ nanopillar rectifiers (~0.008 µm²) require ~32 µW RF input and yield ~0.2 nW DC output; adding DC bias reduces total input below 10 µW. Linearly magnetized STNOs require ~138 µW and output ~5 nW, while vortex STNOs output a few µW with inputs of a few mW; synchronization of multiple vortex STNOs can serve as neuronal activation. A prior multifunctional MTJ stack (sensor/memory/oscillator) was optimized for memory; here, the stack is optimized for oscillator performance to improve inference efficiency. Spintronic devices offer low power, non-volatility, and CMOS integration as evidenced by MRAM commercialization. Vortex STNOs are highlighted for high SNR, reproducibility, low field requirements, larger output power (1–10 µW possible), and low device-to-device variation compared to linear STNOs or spin Hall nano-oscillators.

Device technology and stack: MTJ stack (thicknesses in nm): 5 Ta/50 CuN/5 Ta/50 CuN/5 Ta/5 Ru/6 Ir0.2Mn0.8/2.0 CoFe0.3/0.7 Ru/2.6 Co0.4Fe0.4B0.2/MgO wedge/2.0 Co0.4Fe0.4B0.2/0.2 Ta/7 NiFe/10 Ta/7 Ru on Si/200 nm SiO2. MgO thickness is a wedge across wafer, yielding RA ~3–20 Ωµm²; devices used here have RA ~9 Ωµm², TMR ~60–70%. Geometries: STNOs are circular 300 nm diameter nanopillars forming a vortex free layer. MRAMs are elliptical nanopillars (e.g., 75 nm × 225 nm; also 100 nm × 200 nm for switching tests) providing shape anisotropy for bistability (P/AP states). Free layer thickness is optimized for vortex oscillation; MRAMs are switched via local magnetic field lines above devices. Circuit and operating principle: A minimal WSTNO comprises two MRAM synapses and one STNO neuron connected in a resistive network. Inputs are analog voltages V1, V2 applied to MRAMs whose conductances Gi (inverse of Ri) realize weights (non-volatile via P/AP states). A DC bias current IBias is added in parallel. The total STNO excitation current is I_STNO = (ΣViGi + IBias) R_parallel / R_STNO, where R_parallel = (ΣRi^-1 + R_STNO^-1)^-1. Branch current in MRAM i: Ii = ViGi − I_STNOR_STNO/Gi. In the limit R_STNO ≪ R_MRAM, the neuron output y follows y = f(ΣViGi + IBias), with f given by the nonlinear P_STNO(I_STNO) characteristic (leaky-ReLU-like with threshold at critical current). Experimental setups: Two interconnected probe stations with multiple micro-positioners, three Keithley 2400 SMUs (inputs), a bias-T, and an Agilent E4446A spectrum analyzer (RBW 39 kHz) for RF power integration. Separate in-plane magnetic fields applied in each probe station. No RF amplification used. Oscillation power and frequency obtained by Lorentzian fits to spectra; values reported at 50 Ω load. For MRAM switching probability, a 100 nm × 200 nm nanopillar with a field line a few hundred nm above was driven by a Keysight M8190A AWG plus 42 dB amplifier to inject single pulses; observed on a high-impedance oscilloscope; 1–3 ns pulses used; 100 repetitions per condition; pulse conditions given at the field line. WSTNO characterization protocol: MRAM states set via minor hysteresis loops using in-plane magnetic field (coercivity difference allows setting P-P, P-AP, AP-P, AP-AP). During operation, in-plane fields of about −19 Oe (STNO) and −22 Oe (MRAM) are used; IBias ~3.9 mA. Input voltages V1, V2 swept while measuring STNO integrated RF power P_STNO for all MRAM state combinations. Analytical predictions derived by plugging measured component resistances and P_STNO(I_STNO) into the neuron equation to compare with experiments. Fabrication: Nanopillar patterning via e-beam lithography (nanopillars) and direct-write laser lithography elsewhere; ion beam etching for all etches. Surrounding dielectric SiO2. Top contact: 450 nm AlSiCu; field line: 800 nm AlSiCu.

- STNO performance: Vortex STNOs (300 nm diameter) exhibit critical current ~4 mA with nearly linear increase of integrated RF power beyond threshold up to ~3 µW at I_STNO = 6 mA and oscillation frequency around 240–245 MHz. Maximum P_STNO ~4 µW before MgO breakdown. Typical linewidth at 5 mA across seven devices: 0.7 ± 0.5 MHz. Oscillations obtained with small in-plane field (≈ −19 Oe). - MRAM properties: Elliptical MRAMs show square-like hysteresis with distinct P/AP states at zero field and differing coercive fields. Average resistances across 56 devices (75 × 225 nm): P = 740 ± 277 Ω, AP = 1445 ± 356 Ω. 100% switching probability from P to AP with a single 1 ns pulse ≥ 350 mV applied to a field line (~0.67 kOe for 3 µm width line), corresponding to ~30 pJ; similar to typical field-switched MRAM energies despite stack not optimized for write efficiency. - WSTNO neuron behavior: The integrated output power P_STNO vs inputs (V1, V2) shows nonlinear activation shaped by MRAM states, consistent with leaky-ReLU-like transfer with a threshold at critical current. Experimental P_STNO maps for all four MRAM state combinations (P-P, P-AP, AP-P, AP-AP) reasonably match analytical predictions based on measured device parameters and the circuit model. Example activation thresholds for a 1 µW output-power contour: P-P activates when V1 + V2 > 1.35 V; AP-AP activates when V1 + V2 > 1.46 V; mixed states yield asymmetric activation. - Footprint and energy: Reported small areas and energies. Table 1: MRAM area 0.015 µm² with 1 ns programming energy 30 pJ; STNO area 0.07 µm² with 5 ns operation energy ~25 pJ; WSTNO (2 synapses + neuron) area 0.037 µm² with 5 ns operation energy ~27.5 pJ. Elsewhere in text: ~0.017 µm² per MRAM and ~0.09 µm² per STNO. Non-volatility yields near-zero static power. - System implications and comparisons: Due to high output power (≥3 µW) at low RF frequency (~240 MHz), monolithic CMOS integration is facilitated with minimal amplification. Energy metrics compare favorably in order of magnitude to CMOS neuromorphic platforms (e.g., Intel Loihi: ~120 pJ per synaptic update over 6.1 ns; ~81 pJ/52 pJ per neuron when active/inactive). A network-level simulation (10 STNO neurons with 20 weights each) recognized 4×5 pixel digits (details in Supplementary).

The demonstrated WSTNO validates that non-volatile MRAM synaptic weights combined with a vortex STNO neuron from a single MTJ stack can realize weighted summation and nonlinear activation suitable for neuromorphic inference. Measured P_STNO maps align well with analytical predictions, confirming the circuit model and the leaky-ReLU-like transfer function arising from the STNO threshold. Deviations (notably in mixed P/AP states and along scan direction) are attributed to heating and small irreversible resistance drifts during prolonged measurements; improving MRAM RA or size is expected to enhance stability. The ability to bias the neuron via IBias allows shifting activation thresholds, providing an extra degree of programmability. The system benefits from non-volatility (nearly zero static power) and adequate RF output power for direct CMOS interfacing. Energy per operation for the STNO neuron (~25 pJ in 5 ns) and MRAM programming (~30 pJ for 1 ns) indicate promising efficiency relative to CMOS neuromorphic baselines. The architecture scales naturally: more inputs/weights per neuron, multi-level weights via multiple MRAMs in series, multiple neurons operating in parallel per layer, and multiple layers in series. CMOS peak detector and comparator circuits can convert STNO oscillation to binary spikes, enabling SNN-like operation; envelope detection can support analog ANN outputs at some cost. Frequency-division multiplexing via shared waveguides and techniques such as local optical heating (e.g., integrated VCSELs) present further optimization opportunities.

The paper presents a proof-of-principle weighted spin torque nano-oscillator (WSTNO) built from a single multifunctional MTJ stack, integrating two MRAM synapses (non-volatile weights) and a vortex STNO neuron (nonlinear activation). The device achieves ≥3 µW RF output around 240–245 MHz with low in-plane magnetic field, demonstrates weighted summation with non-volatile states, and exhibits a nonlinear threshold response consistent with analytical modeling. The approach offers small footprint and is compatible with monolithic CMOS integration, promising improved energy efficiency and density for neuromorphic systems. Future work includes: scaling to many inputs and neurons across multiple layers; implementing multi-level synaptic weights via additional MRAM elements; monolithic integration of WSTNO arrays atop CMOS with on-chip peak/envelope detection; reducing variability and improving MRAM stability (e.g., optimizing RA and dimensions); lowering STNO critical current and power via diameter reduction and other stack optimizations; exploring frequency-multiplexed interconnects and optical assistance (e.g., VCSELs).

- Device-to-device variations in MRAM resistances and STNO characteristics may impact precise weight resolution and output accuracy. - Observed deviations in mixed MRAM states and drift along scan direction suggest heating-induced and minor irreversible resistance changes during long measurements; stability could be improved by optimizing RA or lateral sizes. - Operation requires a small in-plane magnetic field (≈ −19 to −22 Oe), necessitating local field generation or equivalent biasing in integrated systems. - Maximum output constrained by MgO breakdown (~4 µW limit in tested devices). The MTJ stack was optimized for oscillation, not for minimal MRAM switching energy. - Reported footprint figures vary within the paper; further process optimization and standardized metrology are needed to consolidate area metrics. - Additional CMOS interface circuitry (peak detector, comparator) introduces power overhead that must be co-optimized in full systems.