Von-Neumann architecture computing is projected to reach its limits within a decade due to power consumption constraints. Neuromorphic computing systems (NCSs), inspired by the brain's parallel processing, offer a potential solution. These systems utilize many parallel processors (neurons) communicating via simple messages (spikes) or continuous interactions (oscillations) mediated by programmable memory units (synapses). The synapses weight individual input signals, which are then non-linearly mapped to an output signal by the neuron. This architecture is characterized by the close proximity of processing and memory units, along with non-volatile memory. While CMOS-based NCSs have shown improvements, they still lag behind the brain in energy efficiency and footprint. New hardware implementations are needed, with spin-based computing emerging as a promising candidate due to its small footprint, low power consumption (resulting from the low intrinsic energy required for nanomagnet manipulation), and non-volatile information storage. MTJs integrated on CMOS are scalable and robust, as evidenced by commercial MRAM technology. The challenge lies in integrating the necessary functionality into a single, scalable, energy-efficient system capable of monolithic integration with CMOS for improved energy efficiency and density. Various devices can implement synapses and neurons, with MTJ nanopillars showing promise but with varying power and frequency requirements. This work proposes a weighted spin torque nano-oscillator (WSTNO) system, combining non-volatile magnetic memories (MRAMs) acting as synapses and non-linear STNOs acting as neurons, all fabricated from a single multifunctional MTJ stack to create a basic programmable computing unit. This approach contrasts with previous NCSs based on MTJs by incorporating non-volatile weights.

The literature extensively covers different approaches to neuromorphic computing hardware. Memristors and photonics have been explored for implementing synapses and neurons. Spin Hall oscillators and MTJs, particularly, show promise in low power consumption and reduced footprint. The existing literature on MTJ-based neuromorphic computing encompasses various implementations of neurons and synapses using MTJ micropillars and nanopillars, exhibiting diverse power and frequency characteristics. Some designs use nanopillars as rectifiers, while others employ linearly or vortex-magnetized STNOs. The synchronization of multiple vortex STNOs has also been proposed as a neuron activation mechanism. The choice of implementation depends on the specific frequency and power requirements. This research builds upon existing work by introducing a novel WSTNO system that combines the advantages of non-volatile MRAMs for synapses and high-output-power vortex STNOs for neurons, all fabricated from a single optimized MTJ stack, improving integration and reducing complexity.

The study uses a multifunctional MTJ stack optimized for oscillator performance rather than memory performance. The stack prioritizes the inference phase of neuromorphic applications where weight writing is a one-time process and doesn't significantly impact long-term energy efficiency. A vortex STNO stack is employed due to its high signal-to-noise ratio, reproducibility, low magnetic field requirements, and large output power. The nanopillar dimensions determine the magnetic behavior of the free layer: diameters above 300 nm result in a vortex magnetization state, while elliptical nanopillars around 125 nm exhibit a uniformly in-plane magnetized free layer suitable for memory applications. The MTJ stack consists of 5 Ta/50 CuN/5 Ta/50 CuN/5 Ta/5 Ru/6 Ir0.2Mn0.8/2.0 CoFe0.3/0.7 Ru/2.6 Co0.4Fe0.4B0.2/MgO wedge / 2.0 Co0.4Fe0.4B0.2/0.2 Ta / 7 NiFe/10 Ta/7 Ru (thicknesses in nm). The MgO thickness is varied, resulting in different resistance area product (RxA) values. Devices with RxA around 9 Ωµm² are used, maximizing oscillation power. The WSTNO concept is demonstrated with a minimal network: two MRAMs and one STNO. Each input (analog voltage source) is weighted by an MRAM's resistance state (high or low). The resulting currents excite the STNO into oscillation. The characterization involved measuring STNO oscillation power and frequency, and MRAM resistance states. The WSTNO system was characterized by measuring its output power as a function of two input voltages, for all possible MRAM resistance state combinations. The experimental results are compared against an analytical model.

The STNO characterization showed output powers above 3 µW and frequencies around 240 MHz in 300 nm diameter nanopillars with a critical current of around 4 mA. The MRAMs exhibited a bi-stable resistance state, programmable using minor loops of an externally applied magnetic field, with a switching energy of 30 pJ. The WSTNO characterization demonstrated a non-linear output power as a function of the weighted inputs, showing good agreement with an analytical model. Deviations were attributed to heating effects and irreversible resistance changes in the small MRAMs during the long measurement period. The activation threshold of the artificial neuron was shown to be programmable based on the MRAM states. The non-volatile MRAMs could be programmed using 1 ns, 30 pJ pulses, and the energy consumed for the oscillation of a single STNO neuron was estimated at 25 pJ in 5 ns. The device footprint was very small compared to CMOS-based artificial neurons. Simulations of a larger network using 10 STNOs with 20 weights each demonstrated successful digit recognition.

The experimental results confirm the successful implementation of a functional WSTNO artificial neuron using a simple network of two MRAMs and one STNO. The non-linear behavior of the STNO, combined with the programmable resistance states of the MRAMs, allows for weighted summation of inputs and a non-linear output response mimicking the behavior of a biological neuron. The relatively high output power (above 3 µW) and low oscillation frequency of the STNO make integration with CMOS technology more feasible. The small footprint of the devices is a significant advantage over existing CMOS-based solutions. The energy consumption is promising compared to state-of-the-art neuromorphic systems, particularly considering the non-volatility of the weights. While some deviations from the model were observed, mainly due to heating effects, the overall performance demonstrates the potential of the proposed WSTNO system for building more complex NCSs. Future work will focus on increasing the number of weighting levels, inputs, and detection levels, and on monolithic integration with CMOS.

This paper successfully demonstrated a proof-of-concept for a WSTNO system, a novel building block for neuromorphic computing. The system utilizes a multifunctional MTJ stack to create non-volatile MRAM synapses and high-power STNO neurons. Experimental results validated the system's functionality and demonstrated its potential for low-power, high-density neuromorphic computation. Future research will focus on scaling the WSTNO for larger, more complex networks and integrating it monolithically with CMOS technology to further improve performance.

The main limitation of this study is the small number of MRAMs and inputs used to demonstrate the WSTNO concept. The observed deviations from the analytical model, attributed to heating and irreversible resistance changes in the nanometer-sized MRAMs, indicate a need for optimization in the MRAM design to improve stability under prolonged operation. The energy consumption comparison with existing systems is not completely direct because the experimental conditions are not identical, and the scalability of the proposed technology remains to be fully tested.