Unprotected sidewalls of implantable silicon-based neural probes and conformal coating as a solution

Implantable neural devices fabricated by microfabrication now span electrical, chemical, optical, multimodal, and microfluidic modalities and have advanced basic neuroscience with potential clinical translation. The Michigan probe is an early impactful example, with later innovations including SOI shank shaping, high channel counts, and CMOS-based microelectrodes. Despite long-term animal studies, there is no FDA approval for multisite silicon-based microelectrodes; by contrast, the Utah Electrode Array is approved for up to one month but has single-site shanks. A critical barrier to human approval is demonstrating long-term reliability and biostability. While top surfaces of microelectronics are typically protected by SiO2, SiN, multilayer stacks, or polymers (Parylene C, polyimide, SU-8), the vertical silicon sidewalls of penetrating multisite devices are commonly left unprotected, as they lack conductors. Silicon corrodes in saline depending on temperature, chemistry, and doping level (e.g., ~36.8 µm/year for undoped Si at 37 °C in bovine serum; heavy doping slows dissolution by ~10×). For microscale devices intended for decades-long implantation, even a few microns/year may lead to failure. Prior sidewall protection efforts are rare; one study applied Parylene C conformally post-release, but required serial laser ablation to reopen sites with a narrow process window. An ideal sidewall protection is batch-compatible and low-temperature to remain compatible with common metals and photoresist. This study explores ALD and ICPCVD SiO2 at ≤130 °C to enable photoresist masking of top features. To assess sidewall coverage, we used KOH wet etching due to its high selectivity for Si over SiO2, so pinholes/defects in protection allow rapid Si etching. We fabricated test devices matching previously validated neural microelectrodes and coated sidewalls with ALD SiO2, ICPCVD SiO2, both, or neither, and compared performance using FIB cross-sectioning, SEM, and 3D extrapolation of etched volumes.

Fabrication and samples: Four groups were made on 100 mm heavily boron-doped Si wafers (0.005–0.02 Ω·cm) with 1 µm thermal SiO2: (1) control (no sidewall protection), (2) ALD-SiO2, (3) ICPCVD-SiO2, (4) ALD+ICPCVD-SiO2. Eight PECVD passivation layers (NONONONO; N=SiN, O=SiO2) totaling 1.85 µm were deposited (STS PECVD). Shanks were defined by 9 µm AZ4620 photoresist (hard bake 100 °C, 30 min) and etched by ICP RIE (90 sccm Ar, 10 sccm C3F8; NLD-570 ICP RIE) through passivation and thermal oxide. DRIE Bosch etching (400 sccm SF6, 1 sccm C4F8; Omega LPX Rapier, SPTS) etched ~80 µm into Si, exposing sidewalls.

Sidewall coatings: ALD-SiO2: ~50 nm SiO2 (1500 cycles) using trismethylaminosilane and ozone in an Anric AT410 at 130 °C, 0.02–0.035 nm/cycle; thickness verified by ellipsometry. ICPCVD-SiO2: ~1323 nm SiO2 deposited 90 min in an Oxford ICPCVD reactor at chuck 80 °C with silane, helium, oxygen; ICP power 1322 W; thickness by ellipsometry. Residual stress of ICPCVD film measured as 32.88 ± 1.58 MPa (compressive) using dual-laser wafer bow on 100 mm wafers (n=4).

Accelerated failure (KOH) test: Rectangular chips (~1.5 × 1.5 cm²) with multiple dies were immersed face-up without agitation in 45% KOH in a beaker on a 60 °C hotplate for 0, 5, or 30 min (N=3 devices per group). KOH has high etch selectivity for Si over SiO2 to reveal pinholes/defects or incomplete coverage.

Imaging and quantification: SEM (Hitachi SU8230) was performed before and after 30 min KOH etch; samples were mounted horizontally, tilted 40°, secondary electrons, WD ~14.5 mm, 2 kV. False coloring was applied in GIMP 2.10. FIB-SEM cross-sections were acquired after sputtering 5 nm Pt:Pd (80:20) coating; FIB systems: FEI Helios 660 or ZEISS Crossbeam (Ga+ source); a protective Pt strap was deposited before milling.

3D extrapolation of etched volume: Tip side-view SEM images were imported into ImageJ to digitize surface points along sidewall edges (with 40° tilt correction). Device CAD (L-Edit layout) was imported and extruded in SolidWorks to match dimensions. Extruded cuts defined by SEM-derived surface points were applied along all sidewalls, assuming the tip side-view profile represents the full sidewall. The etched and non-etched volumes were compared to yield etched Si volume. Statistics: One-way ANOVA (N=3 per group) with Tukey pairwise comparisons at 95% confidence; significance threshold p=0.05 (Minitab 19).

• Visual KOH etch outcomes (front and side SEMs): Bare Si sidewalls etched extensively within 30 min; ALD SiO2 remained largely intact with only a thin exposed band near the top edge after 30 min; ICPCVD protected sidewalls were mostly intact at 5 min but showed roughly half-wall exposure by 30 min; ALD+ICPCVD exhibited partial collapse near the top at 5 min and more exposure at 30 min, with irregular breakdown patterns.
• Quantified etched silicon volume after 30 min KOH (mean ± SD, µm³, N=3): Control 952,381 ± 52,662; ALD 33,682 ± 2,925; ICPCVD 477,898 ± 23,383; ALD/ICPCVD 322,052 ± 18,510. One-way ANOVA p < 0.01; Tukey pairwise comparisons significant for all combinations (95% confidence).
• Protection rank (least etched to most): ALD > ALD/ICPCVD > ICPCVD > Control. ALD reduced etched volume by a factor of 28.27 vs control; ALD/ICPCVD by 2.96; ICPCVD by 1.99.
• Failure modes: FIB-SEM revealed ALD provided conformal, uniform coverage even at hard-to-access top-edge undercuts from DRIE; ICPCVD showed directional deposition with gaps near the top edge that diminished with depth, explaining top-initiated failure. ALD/ICPCVD films showed bulging morphology and gaps near the top and detached in strips following DRIE scallops; high-magnification images showed columnar film structure and strip delamination.
• Stress/adhesion insight: Both ALD and ICPCVD are compressively stressed; combined stress and possibly stronger ALD-to-ICPCVD adhesion than to Si may promote delamination in the dual stack. Measured ICPCVD residual stress: 32.88 ± 1.58 MPa (compressive).
• General observation: Sidewall protection failure initiated near the top edge across groups, likely due to poorer conformality there and/or faster KOH diffusion access at the top.

Protecting silicon sidewalls of penetrating multisite neural devices is an overlooked but critical design consideration for chronic reliability and potential clinical approval. The rapid KOH etch test provides an efficient screening method for coverage quality, identifying pinholes, defects, and unprotected regions much faster than conventional PBS-based accelerated aging. Quantitatively and qualitatively, ALD SiO2 outperformed ICPCVD and the combined ALD/ICPCVD approach due to ALD's self-limiting, highly conformal deposition that covers hard-to-reach geometries, including undercut edges from DRIE. ICPCVD's directionality left gaps near the top edge that allowed undercutting and subsequent film collapse during KOH exposure. The dual ALD/ICPCVD stack underperformed ALD alone, likely due to combined compressive stresses and adhesion contrasts that led to strip-like delamination along DRIE scallops and bulging near top edges. Failure initiated near the top edge for all groups, attributable to reduced conformality and/or enhanced KOH access; ALD's modest top-edge etching suggests diffusion effects can also contribute even with good coverage. These findings align with broader observations that multilayer stacks can sometimes fail earlier than single layers when one layer undercuts another (e.g., reported Al2O3/Parylene C bilayers), motivating careful materials selection and stack engineering. The authors outline a process-integration approach to incorporate ALD sidewall protection in functional devices using top-plane photoresist masking and subsequent anisotropic etch-back of horizontal SiO2 while preserving vertical sidewalls, making the technique broadly applicable to existing silicon-based implantable platforms.

Most silicon-based penetrating multisite neural devices leave Si sidewalls unprotected, posing a risk to long-term reliability. Using a rapid KOH-based failure analysis, ALD SiO2 provided the most effective sidewall protection, reducing etched silicon volume by ~28× versus bare Si and outperforming ICPCVD and an ALD/ICPCVD stack. The study demonstrates a practical, batch-compatible approach to enhance sidewall robustness and a rapid screening methodology for coverage quality. The approach can be integrated into existing fabrication flows for implantable devices. Future work will compare KOH-based screening with standard accelerated aging in PBS and validate ALD sidewall protection in long-term in vivo functional studies.

• The KOH etch environment (45% KOH at 60 °C) is not physiologically representative; it serves as an accelerated, high-selectivity screen for coverage defects rather than a direct predictor of in vivo performance.
• Etched volume quantification relied on 3D extrapolation from tip side-view SEM images, assuming the etched profile is consistent along the entire sidewall; more sophisticated 3D reconstructions could refine accuracy.
• Sample size for quantitative comparisons was limited (N=3 per group).
• The study focused on coverage quality and failure modes rather than long-term electrochemical performance or in vivo validation, which are deferred to future work.