Towards practical quantum computers: transmon qubit with a lifetime approaching 0.5 milliseconds

Quantum computers can outperform classical computers for tasks such as factorization and quantum simulation. Superconducting quantum computing (SQC) is compatible with semiconductor technology and has advanced rapidly, but coherence time remains a key challenge compared with platforms such as trapped ions, cold atoms, and NV centers. Despite orders-of-magnitude improvements to tens or hundreds of microseconds using state-of-the-art transmon designs, coherence times still fall short of error-correction thresholds needed for practical systems. Longer coherence enables higher gate fidelity and deeper circuits. Transmon (and Xmon) qubits are widely used due to good coherence, easy coupling, and readout. They comprise a single or tunable Josephson junction shunted by a large capacitor; commonly, Al–AlOx–Al junctions are made by double-angle evaporation, and capacitors are planar. Interactions (charge/flux drives, couplers) are tuned to realize qubits. Multiple superconductors have been explored (Nb, Al, Ta; TiN, NbN, NbTiN; granular Al), with Nb and Al prevalent due to mature fabrication. A 2020 Princeton report using alpha-phase tantalum films achieved coherence times exceeding 0.3 ms; they observed wet etching producing better qubits than dry etching. However, dry etching offers advantages (high anisotropy, automation, reduced consumption, hygiene) and is widely used in industry, making it promising for large-scale quantum circuits. Thus, developing a robust dry-etch process for long-lifetime transmons is necessary. In this work, the authors develop and optimize a dry etching process for Ta films, fabricating transmons with very long coherence times, with best T1 reaching 503 μs. They also prepare Nb and Al transmons under identical designs and processes for comparison.

The paper reviews prior progress in superconducting qubits, highlighting transmon/Xmon architectures as standard due to favorable coherence and control. It surveys materials explored for superconducting circuits, including elemental metals (Nb, Al, Ta) and nitrides/carbides (TiN, NbN, NbTiN) and granular Al. It cites a key 2020 result from Princeton where alpha-phase tantalum films yielded transmon coherence times above 0.3 ms, with wet-etched devices outperforming dry-etched ones. The authors motivate dry etching for scalability and process control and position their work as addressing the need for a robust dry-etch Ta process to achieve long lifetimes.

Design: Fixed-frequency single-junction transmons to suppress flux noise. Circuits were minimized to two necessary electrodes without dedicated individual control lines to reduce environmental coupling. Two transmons are dispersively coupled to readout resonators, which couple to a common transmission line for drive and readout. Large-area shunt capacitors were used to reduce electric field density and surface participation, following designs similar to Princeton/IBM. Fabrication: Base metal films (Nb, Al, Ta) ~120 nm were deposited on chemically cleaned and annealed sapphire substrates (pre-heated 100 °C; further degassed 200 °C for 2 h in load-lock before deposition). Nb and Ta were deposited by magnetron sputtering; Al by e-beam evaporation. Device structures (pads, resonators, etc.) were patterned by UV lithography (single-layer 1518 resist) and dry-etched using either inductively coupled plasma (ICP) or reactive ion etching (RIE). Al Josephson junctions were fabricated by e-beam evaporation; prior to junction deposition, an RF ion source desorbed native oxides on the base metal to ensure superconducting contact. After dicing, liftoff in NMP removed resist and unwanted Al; chips were wire-bonded to copper submounts. Film optimization and characterization: Deposition conditions for Ta were optimized to achieve BCC alpha-phase (sputtering pressure, rate, target–substrate distance, substrate temperature). Achieved properties: Nb RRR(300 K/10 K)=49, Tc=9.1 K; Ta RRR=4.5, Tc=4.2 K. XRD confirmed pure alpha-phase Ta with [110] and [220] peaks, no discernable beta phase. XPS showed surface oxide as Ta2O3 without other components. Dry etch processes: Two optimized recipes were developed: (1) ICP etcher (Oxford PlasmaPro 100 Cobra) with SF6:CHF3=4:1, 4 mTorr, 220 W plasma, 50 W bias, ~180 s for 150 nm; (2) RIE (Samco Covent) with CF4, 15 mTorr, 100 W plasma, ~180 s for 150 nm. SEM images showed comparable, anisotropic etch profiles from both tools. Measurement: Chips from multiple batches were measured in a low-noise dilution refrigerator with careful shielding and filtering (details in Supplementary Methods). Coherence times (T1, T2*, echo) were characterized; CPMG sequences were used to extract extended dephasing times. Comparative measurements were made for Ta, Nb, and Al devices fabricated with the same design and processes. Surface treatments included Piranha cleaning/oxidation steps on some Ta chips to study effects on coherence.

- Achieved best energy relaxation time T1=503 μs for a Ta transmon fabricated entirely with a dry etching process. For Q2 of sample Ta-4, average T1=401 μs with best 503 μs; for Q1 of Ta-3, average T1=359 μs with best 431 μs. - Across nominally identical Ta chips (Ta-2, Ta-3, Ta-4), T1 varied from ~102 μs to 476 μs, indicating sensitivity to fabrication-induced defects and material/interface variations. - Ta qubits outperformed Nb and Al qubits fabricated with the same design and processes, indicating a materials advantage of alpha-phase Ta for coherence. - A CPMG echo experiment on Q2 of Ta-2 yielded T2^CPMG=557 μs, demonstrating extended dephasing times under dynamical decoupling. - Surface treatment matters: Ta-1 (no Piranha dip) exhibited lower T1 than other Ta chips subjected to Piranha cleaning, suggesting that enhanced surface oxidation or impurity removal improves coherence. - XPS identified Ta2O3 as the sole surface oxide; XRD confirmed alpha-phase Ta films. Removing surface oxides (e.g., via HF vapor) and maintaining clean surfaces (e.g., vacuum packaging) are proposed to further improve coherence. - A flip-chip design intentionally increasing metal–air (MA) surface participation led to significantly reduced lifetimes (e.g., T1 ~75 μs), implicating MA interface loss as a dominant decoherence channel in these devices. - A 56-qubit chip fabricated with the same processes showed substantially lower T1, T2*, and other coherence metrics than single-qubit chips, attributed partly to increased environmental/high-frequency noise in multi-qubit measurement setups and less aggressive filtering/attenuation. - Device design exhibited Purcell limits exceeding 1–2 ms, indicating that observed T1 values are not Purcell-limited under the reported configurations. - Dry etching of Ta (both ICP SF6/CHF3 and RIE CF4) produced highly anisotropic profiles suitable for complex, scalable circuit fabrication, supporting manufacturability.

The results address the central goal of achieving long-lived superconducting transmons using scalable, industry-compatible processes. By optimizing alpha-phase Ta films and implementing a robust dry-etch process, the authors achieve T1 up to 503 μs, surpassing typical Nb/Al devices fabricated under identical conditions. Analysis implicates two-level system (TLS) defects at material interfaces as dominant decoherence sources, specifically metal–substrate (MS), metal–metal (MM), and metal–air (MA) interfaces. Controlled experiments increasing MA participation (flip-chip overlay) substantially reduce T1, highlighting MA loss as particularly impactful. Surface chemistry plays a significant role: Piranha treatment correlates with longer T1, suggesting that either enhanced controlled oxidation (forming a cleaner, perhaps more benign Ta2O3) or removal of organic contaminants reduces TLS-related loss. In multi-qubit devices, measurement environment and control requirements introduce additional high-frequency noise that degrades coherence; thus, system-level filtering, attenuation, and isolation become critical for scaling. Since Purcell limits are well above measured T1, improvements should focus on mitigating interface loss (material choice, surface preparation, geometry to reduce participation) and environmental noise. The dry-etch Ta process combines performance with scalability, making it a promising path toward practical quantum processors.

The study demonstrates that transmon qubits fabricated from alpha-phase tantalum using a fully dry etching process can achieve lifetimes approaching 0.5 ms (best T1=503 μs), outperforming comparable Nb and Al devices under the same design and fabrication conditions. The work identifies material interfaces—especially the metal–air interface—as key decoherence sources and shows that surface treatments and participation engineering significantly affect coherence. The dry-etch process provides anisotropic, stable patterning suitable for complex, large-scale quantum circuits. Future work should focus on further reducing interface loss (e.g., selective oxide removal such as HF vapor, improved surface passivation, vacuum packaging), refining fabrication to reduce device-to-device variability, and improving multi-qubit measurement environments to suppress high-frequency noise, with the goal of achieving millisecond-scale coherence times and enabling practical fault-tolerant superconducting quantum computing.

- Device-to-device and chip-to-chip variability is significant (T1 ranging from ~102 to 476 μs across nominally identical Ta processes), indicating sensitivity to subtle fabrication and material-interface differences (e.g., TLS variations, junction/parity effects). - The precise mechanism by which Piranha treatment improves T1 is unresolved (active oxidation vs impurity removal). - Multi-qubit implementations exhibited reduced coherence due to environmental/high-frequency noise and less aggressive filtering necessary for fast control, highlighting system-level limitations not present in single-qubit tests. - While Purcell effects are designed to be negligible, other extrinsic noise sources may still contribute; comprehensive noise budgeting and isolation were not fully detailed. - Affiliations and some process details (e.g., exact junction geometry parameters) are not exhaustively specified in the main text; some data reside in supplementary materials.