The increasing prevalence of artificial intelligence (AI) across diverse environments presents a significant challenge due to its substantial power consumption. This high energy demand often necessitates the deployment of AI in centralized locations like cloud servers or edge servers, limiting its applicability in resource-constrained settings. A promising solution to mitigate this power consumption bottleneck is the utilization of memristor-based systems. Memristors, with their inherent energy efficiency, offer the potential to drastically reduce the power requirements of AI systems, making the development of self-powered edge AI a realistic possibility. This research addresses the critical need for robust and energy-efficient AI solutions for edge devices, focusing on the creation of a self-powered AI system that can operate reliably under the unpredictable power supply conditions typical of energy harvesting sources. The paper investigates the challenges of using unstable energy sources to power analog in-memory computing and proposes a novel solution using binarized neural networks and a digital near-memory computing approach. The context of this research is the growing demand for AI in resource-constrained environments such as remote sensors, wearable devices, and implantable medical devices where battery power is limited or impractical. The purpose is to demonstrate the feasibility and performance of a robust, self-powered memristor-based AI system that can overcome the limitations of traditional analog approaches and operate effectively under fluctuating power conditions. The importance of this work lies in its potential to enable a new generation of self-powered, intelligent sensors for applications in various fields, including health monitoring, environmental sensing, and industrial automation. These applications require energy-efficient AI that can operate autonomously without the need for constant power supply or frequent battery replacements. This could significantly advance the capabilities and scope of AI in areas where traditional power limitations have been restrictive.

Prior research has extensively explored memristor-based neural networks as an energy-efficient alternative to conventional AI architectures. Several studies have demonstrated the feasibility of using memristors for in-memory computing, showcasing their potential for significant power savings. However, most of these implementations rely on analog in-memory computing, which requires a stable and precise power supply to maintain accuracy and reliability. This requirement is incompatible with the inherently unstable and unreliable nature of energy harvesters such as solar cells or thermoelectric generators. The use of binarized neural networks has emerged as a promising strategy for mitigating this problem. Binarized networks, using only binary weights and activations, simplify computations and reduce energy consumption. This approach also exhibits tolerance to memristor variability and noise, which is particularly beneficial in the context of energy harvesting. Existing work on energy harvesting-powered AI often incorporates complex voltage conversion and regulation circuitry to provide a stable power supply to the AI system. However, this approach adds complexity, cost, and reduces the overall energy efficiency. This work differentiates itself by focusing on a robust architecture that can operate directly from a fluctuating energy source without relying on intricate power management schemes.

The researchers fabricated a robust binarized neural network using hafnium-oxide memristors integrated into the back end of a CMOS line. The memristors replaced vias between metal layers and were used to program synaptic weights and neuron thresholds non-volatility. The system comprised four memristor arrays (8,192 memristors each), configurable for two neural network layer configurations (116 inputs, 64 outputs) or a single-layer configuration (116 inputs, 128 outputs). A smaller die with a single 8,192-memristor module offered greater flexibility in memristor access. The 130-nanometer low-power process node was chosen for its cost-effectiveness, balanced analog/digital performance, and wide voltage range, making it suitable for extreme edge applications. To ensure reliable operation under unreliable power supply, a differential strategy was employed. Two memristors per synaptic weight were programmed complementarily (one low resistance state, one high resistance state). A dedicated logic-in-memory precharge sense amplifier performed multiplication and XNOR operations simultaneously, reading memristor states. This differential approach minimized the effects of memristor variability and power supply fluctuations, eliminating the need for compensation or calibration circuits. The system computed output neuron values in parallel, using a pipelined operation involving simultaneous threshold reading, sequential input presentation, and integer digital population count circuits for accumulation. Near-memory computing minimized energy consumption by transmitting only binarized activations. The non-volatile synaptic weight storage allowed for immediate inference after power cycling. Level shifters handled the high voltages (4.5 V) needed for the memristor forming operation, while a power management unit and a state machine provided overall system control. The system's functionality was characterized across a wide range of supply voltages and frequencies. Measurements were conducted using a dedicated printed circuit board (PCB), connecting the chip to a microcontroller, waveform generator, and oscilloscope. The energy consumption was measured by varying supply voltages and frequencies. Simulations, using the process design kit and commercial tools, provided insights into different energy consumption sources. Accuracy was assessed by programming memristor arrays with weights and thresholds and testing them with diverse neuron inputs. Schmoo plots showed accuracy variation with supply voltage and frequency. Experiments examined neuron accuracy with varying preactivation values and supply voltages. An analog in-memory computing design was simulated for comparison to demonstrate the robustness of the proposed approach. To evaluate the system's suitability for energy harvesting, a miniature AlGaAs/GalnP heterostructure solar cell was used. The solar cell's current-voltage characteristics were measured under standard and low-illumination conditions. The binarized neural network was directly connected to the solar cell (without interface circuitry) to assess its performance under harvested energy. Accuracy was measured with varying neuron preactivation and solar cell illumination. For neural network evaluation, a mapping technique subdivided neural network layers into binarized arrays, using majority voting to obtain output neuron values. MNIST and CIFAR-10 image classification tasks were used for evaluation, incorporating measured error rates into neural network simulations. t-distributed stochastic neighbor embedding (t-SNE) analysis visualized the impact of low illumination on classification accuracy.

The fabricated memristor-based binarized neural network demonstrated robust operation across a wide range of supply voltages and frequencies without calibration. The measured output matched register-transfer-level simulations. Energy consumption could be reduced by decreasing the supply voltage, showing direct proportionality to the square of the supply voltage. Significant energy was consumed by the on-chip digital control circuitry, but this proportion is expected to decrease in larger systems. The actual multiply-and-accumulate operations consumed a modest 6.5% of the energy. Accuracy was high (near 100%) at supply voltages of 1V or higher. At lower voltages (0.9V), occasional errors occurred, primarily due to memristor variability and sense amplifier limitations. Errors were absent when the neuron preactivation exceeded five. The differential nature of the sense amplifier allowed for accurate weight determination even with memristor resistance deviations. The analog in-memory computing design simulation confirmed the robustness advantage of the digital approach, especially at lower voltages. Using a miniature wide-bandgap AlGaAs/GalnP heterostructure solar cell, the circuit performed comparably to a lab power supply under high illumination (8 suns). Even under very low illumination (0.08 suns), the circuit remained functional, transitioning to an approximate computing mode with increased error rates primarily for low-magnitude preactivation values. Neural network simulations, incorporating measured error rates, showed that the MNIST accuracy was minimally affected by bit errors even under low illumination, while CIFAR-10 accuracy was more significantly impacted. t-SNE analysis showed that misclassified images under low illumination were predominantly difficult-to-classify cases, indicating a graceful degradation of performance. Energy efficiency under optimal conditions (10 MHz, 0.7V) was 2.9 TOPS/W, reaching 22.5 TOPS/W with clock gating and optimized read operations and an estimated 397 TOPS/W in a 28-nm process. The system’s non-volatile memristors maintained data even with low power, unlike static RAMs, and exhibited near-immunity to read disturbance. The direct connection to the solar cell without an interface circuit highlights the circuit's robustness. The overall findings demonstrate the feasibility and advantages of a self-powered, memristor-based AI system for edge applications.

The results show a unique behavior in the system's ability to solve tasks of varying complexity under different energy availability levels. For simpler tasks like MNIST digit recognition, accuracy remained high even under low-power conditions. For more challenging tasks such as CIFAR-10 image classification, accuracy decreased as energy availability reduced, but the system didn't fail completely. This adaptive approximate computing capability stems from the robustness of the memristor read operations and the inherent robustness of binarized neural networks to weight errors. Even in cases of failed memory reads due to low power, the impact on classification was limited. The system mainly misclassified images that were already difficult to distinguish. The use of memristors offers significant advantages over conventional RAM in low-power scenarios because of their non-volatility and immunity to read disturbance. Energy efficiency, while not surpassing state-of-the-art analog systems, is enhanced through clock gating and process node scaling, closing the gap considerably. The authors discuss the need for additional functionalities (data formatting, storage, communication) to be integrated in a future commercial version. Although their circuit can operate with low voltages, future optimization could include on-chip voltage boosting circuits to further broaden compatibility with various energy harvesters.

This research successfully demonstrated a robust, self-powered memristor-based binarized neural network operating from a miniature solar cell, even under low illumination. The digital near-memory computing approach, employing complementary memristors and a logic-in-sense-amplifier, enabled operation without calibration, showcasing high accuracy under optimal conditions and graceful degradation under low power. The system's ability to handle tasks of varying complexity and adapt to energy scarcity positions it as a promising solution for self-powered AI at the edge. Future work could focus on integrating additional on-chip functionalities, optimizing for lower voltage operation, and exploring the application of this approach to other AI tasks and energy harvesting sources.

The current implementation uses a 130nm process node, limiting energy efficiency compared to more advanced nodes. The energy efficiency estimates depend on simulations and might vary in practice. The use of a halogen lamp for illumination during solar cell testing introduces variations from standard AM1.5G illumination, potentially impacting the generalizability of the results. The study focused on fully connected and convolutional neural network architectures. The generalizability to other architectures needs further investigation. The mapping technique used for larger neural networks introduces a slight accuracy reduction. The system does not yet include on-chip input buffering or dedicated convolution circuits, which would be needed for a final commercial product.