Neural signal analysis with memristor arrays towards high-efficiency brain-machine interfaces

The study addresses the growing mismatch between the rapidly increasing number of neural recording channels in brain–machine interfaces (BMIs) and the limited signal-processing capability of conventional CMOS, von Neumann architectures. Traditional pipelines digitize, compress, and process analog neural signals, incurring power, latency, and potential information loss. The authors propose leveraging memristors—devices whose ion-driven conductance changes mimic synaptic behavior—to perform in-memory, analog, parallel computation that is closer to the brain’s processing paradigm. The core research question is whether memristor arrays can efficiently preprocess and decode neural signals, preserving accuracy while dramatically improving power efficiency. The work demonstrates a memristor-based FIR filter bank and a perceptron classifier for identifying epilepsy-related brain states from local field potentials (LFPs), aiming to enable scalable, low-power BMIs.

Prior BMI systems rely on CMOS ASICs with digitization and compression, which can be power-hungry and induce delays (e.g., wireless compressed sensing systems, streaming PCA chips, low-power decoders). High-density probes now offer thousands of channels, intensifying the need for scalable processing. Bioinspired strategies have improved invasive neural probes, suggesting benefits from biomimetic electronics. Memristors have been widely studied for neuromorphic computing due to synapse-like plasticity, analog programmability, crossbar parallelism, and nanoscale scalability. Although memristor-based FIR filters have been proposed in simulations and a 6-tap experimental demonstration exists, practical long-tap, multi-band implementations were lacking. Frequency bands in LFPs (δ, θ, α, β) are known biomarkers for various brain states, including epileptic activity, and prior works have exploited band-limited features for seizure detection and BMI decoding. This study builds on these insights by experimentally implementing a long-tap, multi-band FIR filter bank and a neural classifier directly on memristor arrays.

Hardware and devices: A 1k-cell TiN/HfOx/TaOy/TiN memristor array in a one-transistor-one-resistor (1T1R) structure fabricated on a 0.13 µm CMOS process was used. Devices exhibit bidirectional analog switching and good I–V linearity across conductance states, enabling accurate mapping of weights and direct analog readout without additional signal conversion. Differential pairs of memristors represent signed weights. Task and dataset: Epilepsy-related LFP signals were sourced from the University Hospital of Bonn dataset. For each of three classes—normal, interictal, ictal—100 clips of 4096 samples were available. Each clip was divided into six segments of 600 samples (discarding the remaining 496), yielding 600 samples per class and 1800 total samples. Neural signals originally represented as digitized values were transformed to analog voltage pulses for array inputs. FIR filter bank implementation: A four-band FIR filter bank targets δ (0.5–4 Hz), θ (4–8 Hz), α (8–12 Hz), and β (12–30 Hz) bands. Filters were designed in MATLAB; order selection (40–200 tested) led to a 120-order (121-tap) design. Coefficients were mapped to memristor conductances; two devices per coefficient encoded positive/negative values (differential pair). Each 120-order filter used 242 memristors; the full bank used 968 devices. Continuous input neural signals were conditioned and sampled as voltage pulses applied to input columns. The summed output currents provided filtered signals per band at each time step. The mathematical formulation uses y = xH, with H implemented by conductance matrix and outputs realized as I^m(n) = Σ_k V(n−k)[G^m_pos(k) − G^m_neg(k)]. Feature extraction and neural network: From each filtered waveform, five biomarkers were extracted: maximum, minimum, mean, sum of absolute value, and sum of energy. Across four bands, this yields 20 features per sample. Features were amplified/offset in software to voltage inputs, normalized to 0.1–0.3 V. A single-layer perceptron neural network with 21 inputs (20 features + bias) and 3 outputs (normal, interictal, ictal) was used. The memristor implementation required 63 synapses realized with 126 devices (differential). Training used sigmoid activation and backpropagation offline; trained weights for dataset M (features extracted from memristor-filtered signals) were mapped to the array for inference. Dataset split: 70% training, 30% testing; 10 trials for accuracy statistics. Noise and non-idealities: Hardware noise sources (read noise, conductance variations, fluctuations) are inherently included in results since both filter coefficients and synaptic weights reside in memristors. The Bonn LFP signals include real-world acquisition noise. Device conductance distributions across levels were characterized during mapping/read. Power efficiency estimation: A standard one-channel 0.1 s clip sampled at 10 kHz was used for calculation. Memristor read power per device: (0.2 V)^2 × 20 µs = 0.8 µW. With four 121-tap filters using differential pairs and TIA power of 0.50 mW, energy per sample for filtering is 138.7 pJ/sample at 10 kS/s. Perceptron inference energy assumes (0.8 µW × 21 × 2 + 0.10 mW) × 3 × 50 ns per 0.1 s epoch, leading to 0.20 nW/class. CMOS baselines were scaled from published FIR preprocessing (352.0 µW/class) and SVM decoding (199.0 µW/class), totaling ~551.0 µW/class. The memristor-based system totals ~1.4 µW/class.

- Accurate hardware filtering: Mapping of filter coefficients to device conductances (2–20 µS) showed good agreement with targets. The memristor-filtered outputs matched software results closely. Aggregate filter error across four bands: mean μ = −0.1 µV, standard deviation σ = 1.3 µV. Per-band example errors: δ: μ ≈ −0.8 µV (σ ≈ 0.9 µV); θ: μ ≈ 1.5 µV (σ ≈ 0.9 µV); α: μ ≈ −0.9 µV (σ ≈ 1.0 µV); β: μ ≈ −0.2 µV (σ ≈ 0.7 µV). Errors were small relative to input signal amplitudes (e.g., σ < 1.7% of peak-to-valley in normal signals). - Brain state identification: With 540-test-sample evaluation, software-trained software-inferred (S.S.) accuracy: 96.41% ± 0.39%; software-trained on memristor-filtered features (M.S.): 95.78% ± 0.27%; memristor-implemented network trained on memristor-filtered features (M.M.): 93.46% ± 0.44%. - Power efficiency: Memristor-based system achieved ~1.4 µW/class, versus CMOS estimations of ~551.0 µW/class, yielding nearly 400× improvement. Most power in the memristor system was consumed by the FIR filter bank; the perceptron decoder contribution was small. - Device performance: Memristors exhibited bidirectional analog switching and linear I–V characteristics across conductance states, enabling accurate analog-domain computation without digitization and supporting reconfigurability of filter bands. - Robustness: High identification accuracy was achieved despite hardware noise and real-world recording noise, indicating resilience of the approach.

The work demonstrates that memristor arrays can process neural signals directly in the analog domain to both extract frequency-band information via long-tap FIR filtering and perform classification via an in-memory perceptron. The approach addresses key BMI challenges—power, latency, and scalability—by eliminating costly A/D conversion and memory-processor data movement inherent to von Neumann architectures. The high fidelity of hardware filtering ensures that frequency-domain biomarkers are preserved sufficiently for accurate brain state identification. The modest accuracy drop from software to full hardware inference is attributed to device non-idealities and finite network capacity; it is expected to diminish with larger neural networks or improved training/mapping strategies. The substantial power-efficiency gain (∼400× over CMOS baselines) highlights the potential of memristor-based, in-memory analog computing for future, fully implanted BMIs with many channels, enabling real-time, low-power operation.

This study presents an experimental memristor-based neural signal analysis system that integrates a four-band, long-tap FIR filter bank and a single-layer perceptron to identify epilepsy-related brain states from LFPs. The system attains ~93.46% classification accuracy while delivering ~1.4 µW/class power efficiency—about 400× better than CMOS-based counterparts—enabled by direct analog processing and in-memory computation. The results validate memristor arrays as a promising hardware substrate for high-throughput, low-power neural signal processing in next-generation BMIs. Future work includes mitigating device non-idealities via device engineering, scaling to deeper/larger networks and more complex decoders, implementing on-chip biomarker extraction with memristor-based circuits, and monolithic integration with state-of-the-art neural probes toward fully implanted BMIs.

- The demonstration is not a fully integrated BMI; neural probes were not physically integrated in hardware. - Feature extraction (biomarker computation and normalization) was performed in software for simplicity; on-chip analog implementations were not realized in this work. - The classifier is a simple single-layer perceptron; more complex networks may further improve accuracy and robustness. - Accuracy degradation in hardware (M.M.) reflects non-ideal device characteristics (conductance variations, read noise) and limited network capacity. - Evaluation used a standard LFP dataset (Bonn) with offline segmentation and single-channel processing; real-time, multi-channel scalability and in vivo performance require further validation. - Power estimates rely on modeled TIA power and scaled comparisons to CMOS literature, not measurements from a fully integrated system.