Multi-neuron connection using multi-terminal floating-gate memristor for unsupervised learning

The study addresses a central challenge in neuromorphic hardware: enabling multi-neuron connections that emulate both synaptic plasticity and neuronal membrane potential dynamics using memristive devices. While two-terminal and three-terminal memristors and memtransistors have demonstrated synaptic functions and partial neuron-like behaviors (e.g., integrate or fire), they lack sufficient terminals or an effective capacitive element to emulate multi-connected neuronal membranes. The authors propose a multi-terminal floating-gate memristor (MT-FGMEM) leveraging graphene’s tunable Fermi level to enable charge storage and modulation across multiple, horizontally distant electrodes. The purpose is to realize accurate spike integration (LIF), multi-neuron connectivity (temporal and spatial summation), and unsupervised learning (via STDP+LIF) in hardware, with improved linearity, retention, and energy efficiency compared to existing MT-MEMs. This work is significant for advancing neuromorphic systems capable of label-free learning and scalable, energy-efficient spiking neural networks.

Prior works show two-terminal memristors (e.g., PCM, Mott) can implement partial neuron functions such as integration and firing through device interactions, and capacitive neural networks using volatile memristors offer full LIF but are limited in connectivity due to few terminals. Early MT-MEMs (increasing terminals to 5–6) based on polycrystalline TMDs and MoS2 phase transitions achieved heterosynaptic plasticity by controlling multiple channel conductances via a single drain but could not emulate multi-connected neuron membranes due to the absence of a charge-storage capacitor. Graphene-based floating-gate memories have shown large on/off ratios and memtransistor behavior, and floating-gate devices have been explored for linear synaptic updates. However, a device architecture enabling multi-terminal charge control for both synaptic weight updates with ideal linearity and neuronal membrane integration across multiple connections remained unmet. This work builds on these advances by using a shared graphene floating gate to support multi-electrode charge/discharge and linear triode-region operation for accurate integration.

Device architecture and materials: The MT-FGMEM is a van der Waals heterostructure comprising monolayer MoS2 (semiconductor channel), h-BN (tunneling insulator, 4–8 nm), and monolayer graphene (floating gate, FG), with five terminals (V1–V5) on MoS2 sharing a common graphene FG. The graphene’s variable Fermi level enables enhanced band bending in h-BN and efficient charge tunneling versus metal FGs. Devices also operate as memtransistors with an additional back gate when needed. Operation principle: Applying positive/negative spikes at selected electrodes induces hole/electron tunneling into the shared graphene FG, which diffuses across the FG, modulating conductance of multiple MoS2 channels simultaneously. Readout is at low V_DS (e.g., 10 mV). Linear dependence of I_D on V_FG in the triode region (V_G > V_DS + V_T) enables linear potentiation. Spike-based multilevel memory: After full erase (continuous −6 V on V1), sequential spikes (e.g., +6 V, 0.01–0.1 s on V2) incrementally charge the FG. FG potential and channel current increase stepwise; step size depends exponentially on spike amplitude and width. Calculated FG parameters: C ≈ 1.3 pF; ΔQ ≈ 66.5 fC per level (ΔV_FG ≈ 0.05 V); charging energy E ≈ 3.3 fJ per spike. Neuron implementation (LIF): A comparator is connected to the FG to implement thresholding (V_th). Positive spikes from multiple inputs increase V_FG; negative spikes decrease it. When V_FG exceeds V_th, comparator output switches to a negative feedback (V_EE ≈ −7 V) to reset V_FG, generating a post-spike. Leaky behavior is realized by reducing h-BN thickness to 4 nm, enabling charge leakage (exponential decay) for natural reset. Temporal summation is tested by repeated spikes from one input; spatial summation by synchronized spikes from multiple inputs. Synapse-neuron unit and STDP: Synapse receives V_pre at terminals (e.g., 3.5 V); current I_mem = V_pre × G charges the neuron FG for integration. Post-spike V_post provides feedback to both neuron FG (reset/WTA) and synapse FG (weight update). STDP arises from overlap of V_pre and V_post at the synapse (V_net up to ~5.5 V), enabling potentiation; conductance change follows ΔG = α e^(−βV) for device characterization and ΔG = α e^(−t/τ) for simulation modeling. Experiments mainly use potentiation for learning. Neurosynaptic array (experiment): A 3-neuron × 9-synapse-per-neuron array is fabricated using CVD graphene (FG), ALD Al2O3 tunneling barriers (8 nm synapse FG, 4 nm neuron FG), and CVD MoS2. Spatial summation reliability and V1-like line-orientation training/classification are demonstrated using electrical spikes (3 V, 50 ms). Neuron selection for training is controlled via comparator threshold (V_th = 1.0 V for training, 1.5 V otherwise). Conductance is read via ammeter during classification. Simulation of SNN (unsupervised): A network with 784 inputs and 10–100 post-neurons uses STDP, LIF, and WTA. Synaptic G initialized to small random values; only the neuron with highest integrated input fires per pattern (lateral inhibition). Potentiation per STDP (ΔG = α e^(−t/τ)); homeostatic plasticity is modeled by slightly increasing V_th of firing neurons. Training uses 60,000 unlabeled MNIST samples; testing on 10,000 samples evaluates accuracy. Fabrication details: Stacked graphene/h-BN/MoS2 are assembled via wet/dry transfer; electrodes (Cr/Au) patterned by e-beam/photolithography; ALD Al2O3 as tunneling insulator and spacers; annealing at 300 °C in H2/Ar reduces interface contamination. Array interconnects formed via RIE etching of Al2O3 where needed. Electrical characterization performed with probe stations, source/measure units, and a commercial comparator.

• MT-FGMEM exhibits high on/off ratio >10^5 with stable multilevel retention over 1000 s (~10,000× higher than other MT-MEMs at the same retention), and extends to ~10,000 s retention and endurance over 10,000 two-level cycles and 2000 multilevel spikes.
• As a memtransistor with gate bias (V_g = −40 V), on/off ratio reaches ~10^10.
• Linear potentiation with ideal nonlinearity factor β = 0 is achieved due to triode-region operation (I_D ∝ V_G for V_G > V_DS + V_T). The measured transfer characteristics match FET theory, yielding linear synaptic weight updates and accurate spike integration.
• Spike-based multilevel memory: controllable step size via spike amplitude and width; FG parameters C ≈ 1.3 pF, ΔQ ≈ 66.5 fC per level, per-spike charging energy ≈ 3.3 fJ.
• Neuron LIF: Temporal and spatial summation demonstrated. Temporal: V_FG exceeds V_th after series of spikes (e.g., five-series spikes >0.7 V). Spatial: synchronized spikes from multiple inputs exceed V_th (e.g., three spikes >1 V). Refractory period ~1 µs (comparator delay).
• Energy: Integration energy reduced from 11.7 µJ (Si-IC) to 150 pJ (MT-FGMEM); firing energy comparable to Si-IC (≈250 pJ vs. 286 pJ).
• V1-like line orientation classification (experimental array): Training with 40 sequential spikes per pattern yields selective potentiation of synapses corresponding to the trained orientation; conductance for trained direction diverges increasingly from untrained directions with epochs.
• Unsupervised SNN simulation on unlabeled MNIST: Accuracy depends on synaptic nonlinearity and number of post-neurons. Best accuracy 83.08% at 100 post-neurons with ideal linearity (β=0). Accuracy improves from 47.88% (10 neurons) to 68.08% (30 neurons) and continues to rise with more neurons. Increased nonlinearity (β>0) degrades accuracy by blurring learned weight patterns.

The MT-FGMEM’s shared graphene floating gate enables multi-terminal charge control, allowing multiple pre-neuron inputs to modulate a common membrane potential, thereby emulating temporal and spatial summation akin to biological neurons. The linear triode-region transfer characteristic (I_D ∝ V_FG) translates FG potential increments into proportional channel current, yielding ideal synaptic potentiation linearity (β=0) and precise spike integration. These properties directly address limitations of prior MT-MEMs that lacked a capacitive membrane analog for multi-neuron connectivity. The leaky behavior realized by thinning the tunneling barrier provides natural membrane discharge, completing LIF dynamics without complex circuitry. Experimentally, integrating MT-FGMEM neurons and synapses demonstrates orientation-selective learning analogous to V1 simple cells, validating multi-connection operation and spike-based learning. Simulations confirm that linear synaptic updates and sufficient neuron diversity are critical for unsupervised accuracy on complex data, with β=0 and larger neuron counts yielding clearer receptive-field-like weights and higher recognition rates. Energy analysis shows dramatic savings for integration compared to Si-IC implementations, indicating potential for scalable, low-power neuromorphic systems.

This work introduces a multi-terminal floating-gate memristor leveraging graphene’s tunable Fermi level to realize multi-neuron connectivity, ideal linear synaptic potentiation, and accurate LIF neuron behavior in hardware. The device achieves high retention and endurance, large on/off ratios (up to 10^10 with gating), and low energy integration (150 pJ). A small neurosynaptic array experimentally performs V1-like line orientation learning, and network simulations on unlabeled MNIST reach 83.08% accuracy with 100 post-neurons at ideal linearity. These results establish MT-FGMEMs as promising building blocks for energy-efficient, label-free neuromorphic computing. Future directions include implementing hardware homeostatic plasticity for fully unsupervised on-chip learning, enhancing tunneling insulators to further reduce spike amplitudes/durations and energy, scaling arrays while managing interconnect parasitics, and handling asynchronous, stochastic spiking to combine temporal and spatial summation during learning.

• The experimental neurosynaptic array training uses threshold-controlled neuron selection (supervised selection) rather than fully unsupervised learning; full unsupervised operation is shown only in simulation with modeled homeostatic plasticity.
• Input spikes in experiments are synchronized, so learning relies on spatial summation; temporal-spatial interactions under stochastic spike timing (common in biology) are not fully demonstrated.
• STDP experiments and simulations primarily employ potentiation; depression dynamics are not emphasized, potentially limiting bidirectional plasticity evaluation.
• Demonstrations are at modest array scale (3 neurons × 9 synapses per neuron) for the hardware experiment; MNIST results are simulation-based.
• Reported energy reductions (e.g., 150 pJ vs. 11.7 µJ) primarily refer to integration energy; comprehensive system-level energy under varied workloads remains to be evaluated.