Inkjet-printed low-dimensional materials-based complementary electronic circuits on paper

CMOS technology, using complementary n-type and p-type field-effect transistors, underpins modern digital and analog electronics due to low power dissipation, full logic swing, and large noise immunity. As electronics moves toward ubiquitous, flexible, and wearable applications (IoT, smart packaging, health monitoring), CMOS must be adapted to physically flexible, stretchable substrates. Organic semiconductors have enabled flexible CMOS circuits but face limitations in mobility, stability, and electrical behavior. Low-dimensional materials, including 1D carbon nanotubes (CNTs) and 2D materials such as TMDs (e.g., MoS2), offer promising mechanical and electrical properties for next-generation flexible electronics. Prior CNT-based CMOS inverters on flexible substrates showed progress but with trade-offs in noise immunity and power; 2D-material-based complementary inverters have been mainly on rigid substrates, with limited results on flexible ones. This work addresses these gaps by demonstrating complementary CMOS circuits on paper that combine n-type MoS2 FETs and p-type CNT FETs, leveraging inkjet printing for low-cost, room-temperature fabrication compatible with paper’s constraints. The purpose is to realize low-voltage, low-power logic gates and a basic sequential circuit on an environmentally friendly, recyclable substrate.

• Flexible CMOS using organic semiconductors (e.g., P3HT, TIPS-pentacene, N1100) has achieved low power operation with mobilities ~0.1–5 cm^2/Vs, but further improvements in stability and electrical behavior are uncertain.
• CNTs have been used for CMOS inverters on flexible substrates; e.g., high-gain aerosol-printed inverters on PET showed poor noise immunity and power consumption trade-offs (Xiao et al.).
• Complementary inverters based on 2D materials have been shown on rigid substrates; flexible implementations remain challenging with limited performance.
• Paper is an attractive recyclable, low-cost, flexible substrate but presents fabrication challenges (roughness, hygroscopicity, low thermal resistance), motivating room-temperature, maskless techniques like inkjet printing.
• High-performing inkjet-printed 2D semiconductors (mobility >1 cm^2/Vs) remain challenging; hybrid approaches (CVD-grown channels with printed dielectrics/contacts) can bridge this gap.

Device and materials:

• Substrate: PEL P60 paper.
• Conductors: Inkjet-printed nanoparticle silver ink (Sigma-Aldrich).
• p-type semiconductor: Semiconducting single-walled CNT ink (diluted IsoSol-5100, ~0.053 mg/mL in toluene; Nanolntegris).
• n-type semiconductor: CVD-grown MoS2 patterned into stripes on sapphire and transferred to paper.
• Gate dielectric: Water-based hBN ink prepared from bulk hBN powders; high capacitance per unit area enabling low-voltage operation.

Fabrication (ambient conditions, no annealing/post-treatment):

• Printing tool: Fujifilm Dimatix Materials Printer 2850.
• Silver contacts (source/drain/gate): Single pass, one nozzle, 20 µm drop spacing, room-temperature platen; ~1 pL droplet cartridges.
• hBN dielectric: 2 mg/mL, 20 µm drop spacing, 100 passes; 10 pL droplet cartridges.
• p-type CNT FETs: Top-gate/top-contact; single printed CNT layer to ensure percolation while maximizing ION/IOFF. Channel widths W = 500 µm; channel lengths Lp = 40 µm and 350 µm tested. Silver S/D on CNT network; printed hBN dielectric; printed silver top gate.
• n-type MoS2 FETs: Top-gate/top-contact; MoS2 stripe as channel; printed silver S/D; printed hBN dielectric; printed silver top gate. Channel L = 40 µm, W = 500 µm.

Design considerations:

• Matching n- and p-FET characteristics is critical for CMOS. With identical printed hBN (thus similar CG), current matching is tuned via geometry: selecting Lp/Ln (Lp = 350 µm, Ln = 40 µm; W fixed at 500 µm) compensates differences in mobilities and thresholds.
• Mobility extraction in saturation: µx = (Lx/(Wx·CG·VGSx^2))·(2/IDsx), yielding average µp ≈ 25 cm^2/Vs (CNT FET) and µn ≈ 3 cm^2/Vs (MoS2 FET).

Circuit implementations:

• CMOS inverter: One CNT p-FET and one MoS2 n-FET; designed for VDD ≤ 3 V (tested at VDD = 2 V). Measured VTC, gain, noise margins, and power.
• CMOS NOR gate: Two-input NOR built from the complementary technology; tested at VDD = 3 V with digital inputs at 0/3 V. Steady-state output characterized and dynamic response assessed.
• Hybrid complementary–pass-transistor-logic (PTL) D-Latch: Uses six transistors; two CNT FETs as pass transistors (better performance than n-type devices). Measured time-domain response of Q and Q̄ versus data (D) and clock (CLK).

• Device symmetry and performance:

  • p- and n-type FETs show mirror-like characteristics around ground with comparable saturation currents and ohmic contacts (silver to CNTs/MoS2).
  • Threshold voltages approximately 0 V for both devices at |VDS| = 2 V.
  • Extracted mobilities: µp ≈ 25 cm^2/Vs (CNT network FET), µn ≈ 3 cm^2/Vs (MoS2 FET).
  • Geometry tuning (Lp = 350 µm vs Ln = 40 µm; W = 500 µm) effectively balances drive currents.

• CMOS inverter on paper (VDD = 2 V):

  • Rail-to-rail output swing ≈ 98.25% of VDD.
  • Logic threshold VM ≈ 0.9 V (~VDD/2).
  • Voltage gain |dVOUT/dVIN| ≈ 8 at switching.
  • Noise margins: NMlow ≈ 47%·(VDD/2) and NMhigh ≈ 85%·(VDD/2); absolute immunity to noise ≈ 0.47 V at VDD = 2 V.
  • Static average power consumption PSA ≈ 29 nW; low at steady states, peaking near switching. Asymmetry with higher PSAL than PSAH attributed to higher Ioff of p-FET (residual metallic CNTs).

• CMOS NOR gate (VDD = 3 V):

  • Correct truth-table behavior with near-ideal logic levels.
  • Worst-case output swing ≈ 2.8 V (close to 3 V rail-to-rail) for IN1 = 1, IN2 = 0.

• Hybrid complementary–PTL D-Latch:

  • Implemented with six transistors; CNT pass transistors for gating D with CLK.
  • Q follows D when CLK = 0 and holds state when CLK = 1; complementary Q̄ behaves inversely.
  • Non-idealities and limited switching performance observed, likely due to defects in printed dielectric layers.

• Overall:

  • All devices and circuits operate at low supply voltages (≤3 V) suitable for portable power sources (e.g., solar, NFC coupling, thin-film batteries).
  • Performance is already comparable to mainstream organic flexible electronics, with advantages in gain, noise tolerance, and static power.

The work demonstrates that complementary circuits combining 1D CNT p-FETs and 2D MoS2 n-FETs can be realized on challenging paper substrates using room-temperature inkjet printing for contacts and dielectrics, and transferred CVD MoS2 for the n-channel. By adjusting channel lengths to compensate mobility differences, the inverter achieves balanced switching with near-ideal rail-to-rail levels, sufficient gain (~8) for signal regeneration across cascaded stages, and robust noise margins (~0.47 V at VDD = 2 V). The low static power (≈29 nW) and low-voltage operation highlight suitability for battery-constrained or energy-harvested systems.

The successful realization of a two-input NOR gate with output swing near full rails at VDD = 3 V validates scalability to multi-input logic. The hybrid complementary–PTL D-Latch further shows feasibility of sequential logic and memory elements on paper, although switching non-idealities indicate areas for process improvement, particularly in dielectric uniformity and device matching. Overall, the findings address the research aim by proving the viability of low-dimensional-material-based CMOS logic on recyclable paper with performance approaching or exceeding state-of-the-art flexible organic technologies.

The study introduces a complementary technology on paper that integrates inkjet-printed CNT p-FETs, printed hBN dielectrics, printed Ag contacts/gates, and transferred CVD MoS2 n-FETs. Demonstrated circuits include CMOS inverters (gain ~8, ~98% VDD output swing, robust noise margin ~0.47 V at 2 V, static power ~29 nW), CMOS NOR gates with near-ideal logic levels at 3 V, and a compact six-transistor hybrid complementary–PTL D-Latch. These results establish a path toward low-cost, low-voltage, low-power integrated electronics on recyclable substrates.

Future research directions include: improving dielectric quality and uniformity to enhance switching speed and reduce variability; further suppressing metallic CNT content to lower p-FET Ioff; advancing fully printed high-mobility 2D semiconductors; optimizing circuit architectures for noise margin balance; long-term reliability and environmental stability studies on paper; and scaling to more complex integrated systems.

• Paper substrate imposes constraints (high roughness, hygroscopicity, low thermal resistance), complicating device uniformity and reliability.
• Lack of post-processing/annealing may limit contact quality and dielectric performance.
• Asymmetry in inverter static power due to higher p-FET Ioff, likely from residual metallic CNTs.
• Non-ideal switching in the D-Latch suggests defects or non-uniformities in printed dielectric layers (hBN) and general process variability.
• High-performance fully inkjet-printed 2D semiconductors remain challenging; the approach relies on transferred CVD MoS2 rather than fully printed semiconducting channels.
• Dynamic performance and maximum operating frequency are not extensively quantified; further work needed for speed optimization and large-scale integration.