Hexagonal boron nitride (h-BN) memristor arrays for analog-based machine learning hardware

Two-dimensional materials are promising for CMOS downscaling and beyond-CMOS electronics due to their atomic thickness and pristine surfaces, enabling ultra-dense integration. Prior work has shown non-volatile resistive switching (NVRS) in several 2D materials, including h-BN. CVD-grown h-BN is attractive for wafer-scale fabrication and h-BN memristor arrays have been reported. Nevertheless, most demonstrations have emphasized isolated device characteristics (e.g., DC I–V, basic switching) and used relatively slow programming conditions, with little focus on core machine learning primitives. The research question addressed here is whether h-BN memristor arrays can reliably perform analog dot-product operations and support a hardware implementation of a machine learning algorithm (linear regression) with multistate, non-volatile programmability, low voltage operation, and fast pulses. The purpose is to close the gap between device-level demonstrations and functional machine learning hardware using 2D materials, establishing h-BN arrays as viable building blocks for neuromorphic and analog in-memory computing.

The paper situates h-BN memristors within the broader context of 2D materials applied to CMOS scaling and neuromorphic devices. Earlier studies reported NVRS in 2D TMDCs, black phosphorus, graphene, and h-BN. CVD h-BN enables wafer-scale integration, with switching attributed to metal ion penetration along defects/grain boundaries forming conductive filaments. Prior h-BN work showed forming-free bipolar switching, low set/reset voltages, fast switching, and multi-level states, but often under DC or millisecond pulse programming. Memristor crossbars for analog computing rely on dot-product (multiply-accumulate) operations, widely shown with oxide-based RRAM, yet unreported in h-BN arrays. This study addresses that gap by demonstrating dot-product and a stochastic linear regression task in h-BN arrays under nanosecond pulse programming.

Device fabrication: Au/h-BN/Ti memristor arrays were fabricated on 90 nm SiO2/Si wafers. Bottom electrodes (BEs) of 5 nm Cr/35 nm Au with widths/active areas of 3 μm, 20 μm, and 50 μm were patterned by photolithography and e-beam evaporation. Multilayer CVD-grown h-BN (on Cu, ~8–10 nm thick, ~15–20 layers) was transferred to the substrate by wet transfer. h-BN was patterned (oxygen plasma) to expose 100 μm × 100 μm BE pads. Top electrodes (TEs) of 70 nm Ti, matching BE widths, were deposited and patterned by e-beam evaporation and lift-off. Arrays share a common Au BE across multiple devices with independent Ti TEs (e.g., 1×3 and 1×10 configurations). A thin surface oxide on Ti forms in air but was shown not to affect switching (validated against Au-capped TEs). Cross-sectional TEM confirmed h-BN thickness and local defects enabling filament formation.

Electrical characterization: Measurements were performed on a Cascade semi-automatic probe station using a Keithley 4200 SCS. DC I–V used SMUs; pulse programming used a 4225 PMU for pulses and SMUs for reads, switched via a 4225-RPM. For representative I–V cycling (3 μm × 3 μm cells), 100 consecutive cycles were swept with current compliance of 0.1 mA on the positive side and 1 mA on the negative side. Read voltage for state extraction was 0.1 V. Area dependence was evaluated on devices with 3×3, 20×20, and 50×50 μm2 active areas, each cycled 100 times.

Multistate pulse programmability: Devices were programmed using 500 ns pulses. Protocols included sequences of 50 positive pulses followed by 50 negative pulses per cycle, repeated for 100 cycles. After each pulse, a 0.1 V read was applied to record conductance. Retention tests sampled current every second for 100 s at 0.1 V immediately after the last programming pulse; additional long-term retention up to 10^5 s was performed (in Supplementary Information). Energy per programming pulse was estimated as Epulse ≈ 1/2·I·V·tpulse ≈ 125 fJ under the reported fast-switching conditions.

Dot-product demonstration: A two-device array (two TEs, shared BE) was used. Each device’s TE could be connected to either a pulse source (for programming G1, G2) or a DC source for reading. During read, v1 and v2 were applied and total current I was measured at the BE. Test cases included pulsing both memristors, pulsing one, or pulsing none. After programming (e.g., 30 positive pulses), read voltage sweeps V1=V2=Vsweep from −0.15 V to +0.15 V were performed to assess linearity and repeatability.

Stochastic linear regression: The task was to predict startup profit based on marketing and R&D spend using a public dataset of 50 companies. Inputs (marketing, R&D, in k$) were normalized to 0–0.15 V and applied as v1 and v2. A constant offset (intercept) was subtracted from profit so only two coefficients (mapped to G1 and G2) were learned. The prediction used the dot product I = V1G1 + V2G2 measured by SMUs. The error δ = h − y was computed and parameter updates derived from minimizing (δ^2/2) with ΔG = −δ·v. A hardware-compatible update applied a single 500 ns programming pulse per memristor per iteration, with pulse polarity set by sign(ΔG). Learning rate decay was implemented by reducing pulse amplitude by 0.1% each iteration, starting at ±1 V (reaching ±0.67 V after 400 iterations). Control and sequencing were implemented via a Keithley 4200 SCS using a custom script (KULT/KITE).

• Forming-free bipolar resistive switching with stable cycling: 100 I–V cycles on 3 μm × 3 μm devices showed clear SET/RESET transitions with low variability and low voltages (Vset ≈ +1 V, Vreset ≈ −1 V).
• Distinct resistive states: HRS and LRS at 0.1 V read were separated by ~2 orders of magnitude across 100 cycles, evidencing robust bistability.
• Area dependence: HRS decreased with increasing active area (3 → 20 → 50 μm side length), whereas LRS distributions were only minimally affected, consistent with filamentary RRAM trends.
• Multistate analog programmability: Under 500 ns pulses, conductance could be gradually tuned over multiple levels (e.g., ~4 to ~10 μS across sequences of positive/negative pulses) with good cycle-to-cycle repeatability.
• Low programming energy: Estimated Epulse ≈ 125 fJ per 500 ns programming pulse; potentially reducible to attojoule/pulse regimes with lower compliance currents reported elsewhere.
• Non-volatility: Retention was stable over at least 100 s at 0.1 V read after programming; supplementary tests confirmed stability up to 10^5 s.
• Dot-product operation: A two-memristor array realized I = V1G1 + V2G2. After programming, read sweeps from −0.15 to +0.15 V showed linear, repeatable I–V characteristics. Total current magnitude followed expectations for cases where both, one, or none of the memristors were in LRS, validating analog accumulation.
• Hardware stochastic linear regression: Using the 50-startup dataset, a two-parameter model (G1, G2) trained over 400 iterations with single-pulse updates and decaying pulse amplitudes (±1 V to ±0.67 V). Mean squared error decreased over training, and G1, G2 converged to stable values, demonstrating effective learning on h-BN hardware.

The study demonstrates that CVD-grown h-BN memristor arrays can perform foundational analog computations required for neuromorphic and in-memory machine learning. The devices exhibit the necessary characteristics—forming-free bipolar switching, distinct and stable HRS/LRS, multilevel conductance tuning with nanosecond pulses, and stable retention—enabling reliable weight storage. The linear I–V within the read range (±0.15 V) supports accurate dot-product accumulation, a central primitive in analog neural and ML accelerators. Building upon this, the hardware implementation of stochastic linear regression validates that parameter learning can be accomplished directly in the memristor conductances via single-pulse updates with learning-rate decay realized through pulse amplitude control. The reduction in MSE and convergence of G1 and G2 indicate that the array can learn from data and adjust weights appropriately. Collectively, these findings address the research question by moving beyond isolated device behavior to functional ML operations on h-BN arrays, underscoring their relevance for low-voltage, high-speed, and scalable analog computing based on 2D materials.

This work reports wafer-scale fabrication and characterization of Au/h-BN/Ti memristor arrays with CVD-grown multilayer h-BN, showing stable forming-free bipolar switching, clear HRS/LRS separation, and area-dependent behavior. It establishes multistate, non-volatile programmability using 500 ns pulses with low energy per pulse and robust retention. Critically, it demonstrates dot-product operation with linear and repeatable I–V responses and implements a hardware stochastic multivariable linear regression task with single-pulse weight updates and decaying learning rates, achieving convergence on a real dataset. These results mark an important milestone for deploying 2D-material-based memristors in analog ML hardware. Future work should focus on scaling to larger crossbar arrays, reducing device-to-device variability via improved h-BN synthesis/transfer, exploring broader operating windows while maintaining linearity, and extending to more complex learning algorithms and tasks.

• Device-to-device variability remains large, likely due to nonuniformity of the CVD h-BN film; improvements in synthesis and transfer could mitigate this.
• Dot-product demonstration used a minimal two-device array; larger arrays and crossbar-scale evaluations were not shown here.
• Linearity for reliable dot-product was verified over a limited read voltage range (approximately −0.15 V to +0.15 V).
• Training demonstration was limited to two parameters (no explicit bias device) and a relatively small dataset (50 samples).