Neuromorphic computing, inspired by the brain, utilizes artificial neural networks implemented in hardware to address computationally intensive tasks. While the field gained momentum with the advent of memristive devices and deep neural networks, energy efficiency remains a major challenge. Existing resistive neuromorphic systems, using materials like oxides, phase-change memory, spintronic devices, and ferroelectrics, have demonstrated energy efficiencies up to 100 TOPS/W. However, memcapacitive devices, based on capacitive principles, offer the potential for lower static power consumption. While theoretical proposals exist, practical implementations have been limited by challenges such as large parasitic resistance at small plate distances or limited scalability due to large plate distances in existing memcapacitor designs. This paper introduces a novel memcapacitor design based on charge shielding to overcome these limitations and achieve both high dynamic range and low power operation.

The field of neuromorphic computing has seen significant advancements since the 1980s, particularly with the introduction of memristive devices and convolutional layers in deep neural networks. Several resistive neuromorphic systems have been developed, utilizing various materials and exhibiting energy efficiencies up to 100 TOPS/W. These systems rely on analog storage of synaptic weights for multiplication and Kirchhoff's current law for current summation in crossbar arrays. Memcapacitive devices, while theoretically promising for lower static power consumption compared to memristive devices, have seen limited practical implementations due to challenges in achieving a high dynamic range and sufficient scalability. Previous memcapacitor designs using variable plate distance, metal-insulator transition materials, or varying surface area/dielectric constants faced limitations in either dynamic range or scalability.

This research presents a novel memcapacitor device based on charge shielding. The device comprises a top gate electrode, a shielding layer with contacts, and a back-side readout electrode, separated by dielectric layers. The high on/off ratio of electric field coupling (and thus capacitance) is achieved through either total shielding or transmission, enabling high dynamic range. The device's lateral scalability is significantly improved compared to previous designs because the layer thickness can be optimized, with the dynamic ratio primarily dependent on the shielding layer's efficiency. Charge screening depends on the Debye screening length, a linear approximation of a nonlinear differential equation reflecting the actual behavior in semiconductors. A more detailed structure incorporating lateral p+n n+ junctions in the shielding layer allows for symmetric device response for positive and negative gate voltages, crucial for undistorted weight updates in neuromorphic applications. The device can be arranged in a crossbar array for parallel multiply-accumulate (MAC) operations, with the gate electrode serving as the word line (WL), the shielding layer as a shielding line (SL), and the readout electrode as the bit line (BL). An alternating current (AC) voltage is applied to the WL for readout, while writing is achieved through a voltage difference between the SL and WL. Microscale devices were fabricated on a silicon-on-insulator wafer using ferroelectric-assisted charge trapping as the memory principle. Capacitance-voltage (CV) measurements were performed using an AC signal with a DC bias sweep. Analogue value writing was achieved through pulse number modulation, pulse height modulation, and pulse length modulation. A crossbar array was fabricated and used to implement an image recognition algorithm, employing a differential weight topology and a switched capacitor approach for four-quadrant multiplication. The Manhattan update rule was used for training, with a 5x5 pixel image recognition task involving the letters M, P, and I. TCAD simulations, using Synopsys, were performed on a 90nm gate length device, and the results were compared with experimental data. SPICE simulations were conducted to assess scalability to the nanometer regime and energy efficiency, considering various factors like memory technology scalability, sense amplifier sensitivity, and noise level.

The fabricated memcapacitive devices demonstrated a high capacitive dynamic range of ~1:1478 for microscale devices. Analogue value writing was successfully achieved using different pulse modulation techniques. A crossbar array with 156 memory cells was used to perform a 5x5 image recognition task, successfully distinguishing the letters M, P, and I with high accuracy after one training epoch. TCAD simulations of a 90nm device showed a capacitive ratio of 1:90, further scalable to 1:60 for a 45nm device using high-κ dielectrics. This dynamic range is sufficient for 6-8 bit precision. Simulations considering noise levels (kTC noise) showed that the noise is significantly lower than the readout value, indicating a precision of ~7 bits. A significant finding is the superior energy efficiency of capacitive devices compared to resistive devices. SPICE simulations, incorporating parasitic elements, estimated a minimum energy efficiency of 3452.6 TOPS/W in a worst-case scenario with 95% energy recovery and 29,600 TOPS/W in a realistic neural network scenario (one-layer perceptron trained on MNIST database). The experimental results from microscale devices closely matched the simulated data, validating the simulation model. The analysis showed that most of the energy used in memcapacitors can be recovered during discharging, unlike resistive devices where energy is dissipated as heat. This energy recovery enhances the overall efficiency, potentially reaching 1000-10000 TOPS/W.

The findings demonstrate the feasibility of using charge-shielding-based memcapacitive devices for highly energy-efficient neuromorphic computing. The experimental results with the microscale crossbar array and the detailed simulations, showing excellent scalability and high energy efficiency, validate the proposed approach. The superior energy efficiency compared to resistive devices stems from the energy recovery during discharging. The achieved dynamic range is sufficient for practical applications, and the compatibility with CMOS technology ensures manufacturability. The results suggest that this technology could significantly advance neuromorphic computing, potentially reaching energy efficiencies comparable to the human brain.

This paper presents a novel memcapacitor device architecture based on charge shielding, demonstrating high energy efficiency and scalability for neuromorphic computing applications. Experimental results from a 156-cell crossbar array and extensive simulations show promising results in terms of dynamic range, precision, and energy efficiency (potentially reaching 29,600 TOPS/W). Future research could focus on exploring different memory materials, optimizing device fabrication processes for further miniaturization, and investigating more complex neural network architectures for advanced applications. The compatibility of the technology with CMOS fabrication processes makes it highly promising for large-scale integration and commercial applications.

The study primarily focuses on a relatively simple image recognition task. While the simulations suggest high scalability and energy efficiency, experimental validation at the nanoscale remains to be demonstrated. The Manhattan update rule used for training is a simplified algorithm; exploring more sophisticated training algorithms and their impact on performance would be beneficial. The analysis assumes 95% energy recovery; practical implementations might have lower recovery efficiencies due to resistive losses. Finally, long-term reliability aspects (endurance and retention) require further investigation.