Balancing resistor-based online electrochemical impedance spectroscopy in battery systems: opportunities and limitations

The work addresses whether existing active dissipative balancing hardware in battery management systems (BMS) can be leveraged to perform online electrochemical impedance spectroscopy (EIS) for cell diagnostics such as temperature, aging, and detection of abnormal states. Conventional BMS balancing equalizes SoC using resistive (dissipative) elements, favored for cost and space, but typically not designed for precision excitation and sensing required by EIS. The hypothesis is that balancing currents, if sufficiently high and well-controlled, combined with precise voltage measurements, can serve as sinusoidal excitation for EIS. The study frames the context of increasing industrial interest in online EIS, identifies practical constraints (charger interaction, wiring resistance, thermal limits, leakage variability), and motivates a combined hardware-signal-processing approach to reach diagnostic-grade SNR without substantial hardware changes.

The paper situates online EIS as a method for real-time monitoring of battery internal states, enabling early detection of temperature excursions, lithium plating during fast charging, inhomogeneities in series strings, and aging characterization. Prior works highlight typical EIS frequency ranges (10 mHz–10 kHz, with possible higher frequency use), excitation strategies (single-tone vs broadband; multisines generally offering better SNR than chirps), and practical lab targets (~10 mVpp voltage response). It also references float/self-discharge current analyses for balancing design, the importance of four-terminal pair connections for low-resistance precision, embedded implementation challenges, and noise characteristics including pink (1/f) noise dominance at low frequencies. These inform the paper’s design choices for excitation, measurement, and processing.

1. Sizing of active dissipative balancing resistor: The study derives a normalization for comparing balancing resistors across systems via Ω·Ah. Example: Tesla Model S data yield R_bal = 9061.3 ΩAh. An illustrative worst-case design scenario scales a measured high self-discharge rate (~120 μA/Ah at elevated temperature) to a 100 kWh, 400 V NMC pack (270 Ah cell equivalent), giving a leakage delta of 32.4 mA per cell. With a 3 V minimum balancing voltage and 20.83% balancing duty, the computed resistor is 1.93 Ω (521.1 ΩAh), notably lower than the Tesla-derived normalization. Additional selection factors include charger minimal current capability (e.g., CCS minimum 5 A implying very low equivalent resistance if used as design anchor), thermal constraints and cycling-induced reliability, and sense-wire resistance which can dominate precision unless 4-terminal connections are used. The paper quantifies wire resistance for 1 m, 0.05 mm² conductors and shows its large effect versus low cell impedance at 1 kHz, motivating 4-terminal-pair measurement for accurate EIS. 2) Online EIS formulation: Impedance Z(f) is computed via FFT-based evaluation of voltage and current, acknowledging Hermitian properties. Single-tone sinusoidal excitation is preferred for high frequency-domain energy efficiency. 3) SNR and distortion analysis: The study derives ADC quantization noise-limited SNR expressions, crest factor dependence, and the rule-of-thumb 6 dB/bit for single-sine signals. It discusses constraints from number format (fixed vs floating point), sampling jitter SNR limit (SNR_jitter ∝ 1/(fin·τj)), thermal noise (kBTBW), and pink noise dominance at low frequencies. 4) Signal processing for SNR improvement: The authors quantify process gain from reducing input bandwidth (pre-ADC filtering), rolling average across repeated measurements, and FFT size, and combine them to a total noise-floor/SNR expression. This yields equivalences between digital processing parameters and effective ADC resolution. 5) Demonstrator hardware: A modular board was integrated in parallel to a standard BMS in a 42.9 kWh VOLTIA van pack with 20p 18650 LG-Chem MJ1 cells. Targeting ~10 mVpp at 1 kHz for a ~1.5 mΩ 20p block implies ~6.67 App excitation; a 200 mΩ power resistor (PWR247T-100-R200F) with heatsinking and a voltage-to-current converter (op-amp-based) generates the balancing excitation. Sensing uses 4-terminal connection. Key components: DAC AD5541A, ADC ADS8568, two LPC1769 Cortex-M3 MCUs; CAN and 12 V sections galvanically isolated. 6) Measurement protocol: Excitation frequencies: 2, 5, 10, 20, 40, 80, 160, 320, 640 Hz; sampling rates 2.048 kHz and 10.24 kHz; FFT size M=2048; per-frequency excitation ≥1.1 s with 1 s evaluation ensuring integer periods (total sweep ~10.4 s). Raw time-domain current and voltage are logged via CAN; BMS computes the per-tone impedance online; full-spectrum impedance evaluated offline for analysis.

• Processing–resolution equivalence: Quadrupling sampling rate, FFT size, or the number of averaged measurements, or quartering the input bandwidth each yields an SNR gain equivalent to +1 bit of ADC resolution (per the derived SNR expressions and Equation (18)).
• Sense wiring impact: For 1 m, 0.05 mm² aluminum wire, resistance ~530 mΩ causes a 56 mV drop at 106 mA, and can exceed cell impedance by orders of magnitude (e.g., ~3800× vs |Z(1 kHz)|=0.14 mΩ for a 271 Ah LFP cell), necessitating four-terminal-pair connections for accurate impedance measurement.
• Demonstrator feasibility and SNR: At 20 Hz with a single LG MJ1 cell at ~23°C and ~10 App excitation, current amplitude ~4957.56 mA with noise 5.78 mA (SNR ~58.7 dB), voltage amplitude ~170.75 mV with noise 1.33 mV (SNR ~42.1 dB). The full-spectrum impedance (offline) shows strong out-of-band noise, yielding a negative SNR when considering all bins; the targeted tone remains detectable.
• Thermal performance: Demonstrator peak board temperature ~46.9°C under test with heatsinking.
• Frequency coverage and timing: A 2–640 Hz single-tone sweep requires ~10.4 s; broadband could reduce time (~0.5 s) but would lower SNR as per crest factor and energy distribution considerations.
• Scaling to larger parallel groups: Measuring 20p instead of 1 cell reduces voltage SNR by ~26 dB due to lower impedance; achieving 10 mVpp on low-impedance large cells can demand very high currents (e.g., ~71.4 App for a 271 Ah LFP cell at 1 kHz and |Z|≈0.14 mΩ).
• Agreement with references: Trends in |Z| and phase versus SoC qualitatively align with reference measurements, with noise increasing at low frequencies (consistent with pink noise) and larger phase deviations at higher frequencies.

The results support the central hypothesis that active dissipative balancing hardware can be repurposed for online EIS when balancing currents are sufficiently large and voltage sensing is precise. The demonstrator validates feasibility, while quantifying the constraints that most affect measurement quality: wiring resistance (mitigated by 4-terminal connections), thermal limits of balancing resistors and PCB, ADC resolution and jitter, and low-frequency pink noise. The derived SNR framework shows how signal processing (filtering, averaging, larger FFTs, higher sampling rates) can compensate for limited analog performance, enabling diagnostic-grade measurements without extensive hardware redesign. However, frequency–time trade-offs emerge: sequential single-tone sweeps lengthen measurement duration and risk violating LTI assumptions if cell states change; broadband excitations reduce time but at an SNR cost. The findings are relevant for integrating online EIS into mass-market BMS, informing excitation strategies, thermal/mechanical design of balancing elements, and digital processing to maintain accuracy across operating conditions. Potential extensions include computing excitation current from the actuation path (reducing dependence on current measurement SNR), and model-based interpretation (e.g., equivalent circuit models) for temperature, SoC, and state-of-health estimation.

The study analyzes and demonstrates the use of dissipative balancing resistors for online EIS in batteries. It provides a resistor-sizing framework considering self-discharge, charger constraints, thermal and wiring effects, and presents a general SNR formulation that links ADC resolution with digital signal processing parameters (sampling rate, averaging, FFT size, and input bandwidth). A modular demonstrator confirms feasibility, achieving usable SNR at practical excitation levels and frequencies, with thermal performance within limits, and measurement trends aligning with reference lab equipment. The approach can enable embedded diagnostics (temperature, SoC, state-of-health) without major hardware additions, enhancing safety, reliability, and sustainability. Future work should optimize excitation strategies (multi-tone/broadband vs single-tone), refine noise models (including pink noise and jitter), integrate current computation to improve impedance SNR, and develop standardized normalization for balancing resistor comparisons across chemistries and system architectures.

• Hardware not optimized for weight, volume, or cost; demonstrator-level implementation.
• Thermal constraints and mechanical reliability (thermal cycling) limit minimum resistor values and sustained balancing currents.
• Sense-wire and connector resistances can dominate low-impedance measurements; requires four-terminal-pair connections for precision.
• Low-frequency measurements are noise-limited (pink noise), reducing SNR; high frequencies stress hardware bandwidth and jitter limits.
• Sequential single-tone sweeps (~10.4 s) risk violating linear time-invariance if the system changes during measurement; negative impact on impedance validity unless checked (e.g., Kramers–Kronig).
• ADC resolution, number format, and sampling jitter set upper SNR bounds; processing gains cannot recover clipped or highly distorted signals.
• Self-discharge rates used for sizing include worst-case assumptions; more comprehensive characterization across chemistries and conditions is needed.
• Normalization of balancing resistor sizing across systems/chemistries lacks standardization, complicating comparisons.
• Voltage drop compensation during balancing and strategy-dependent availability of balancing time affect generalizability.