Atomic-scale tuning of ultrathin memristors

The study addresses the challenge of precisely tuning memristor performance at the atomic scale for neuromorphic computing, where integrating memory and processing in memristive devices can overcome the Von Neumann bottleneck. Memristors typically rely on conductive filament formation driven by oxygen vacancy (V_O) migration within a bilayer dielectric (M1/M2). Conventional fabrication often introduces unintended defects (e.g., interstitials, metal vacancies, nonuniform V_O clusters) and defective metal–insulator interfacial layers (ILs), which cause leakage, variability, and necessitate thicker oxides (4–12 nm), complicating mechanistic understanding and limiting scalability. The authors propose using pristine ALD-grown Al2O3 on Al with a negligible IL as a starting point, then introducing controlled MgO atomic layers to tune V_O concentration and electronic structure. DFT predicts Mg doping lowers the Fermi level (increasing HRS) and reduces V_O formation energy (promoting switching). The goal is to realize ultrathin (≈1.2–2.4 nm) memristors with atomically tunable parameters and dominant tunneling conduction in HRS.

Prior work demonstrated memristive switching in various metal oxides (TiO2, HfO2, TaOx, Al2O3, ZnO, WOx, etc.) with acceptable on/off ratios in the 10^2–10^3 range and in some cases up to 10^5–10^6, switching as fast as ~100 ps, and endurance up to ~10^12 cycles. However, many devices rely on poorly controlled defect structures and thick films to suppress leakage, leading to multiple, often conflated conduction mechanisms (Schottky emission, Poole–Frenkel, trap-assisted tunneling, direct tunneling) and variability. Interfacial layer defects (e.g., native oxides from air exposure or poor ALD nucleation on noble metals) are especially problematic, degrading barrier height and uniformity. Earlier work by the authors showed that pristine ALD Al2O3 on Al yields higher, thickness-independent tunnel barrier heights (up to 1.0 eV higher than with defective ILs) and hard breakdown, suggesting a clean platform to which controlled V_O can be added for memristive behavior. This motivates atomic-scale defect engineering via MgO insertion layers to achieve tunable memristor performance.

Device fabrication: Ultrathin Pd/M1/M2/Al memristors were fabricated using an integrated in vacuo system combining DC magnetron sputtering and ALD. Al bottom electrodes were sputtered (Ar plasma; base pressure <5×10^-7 Torr; 14 mTorr/90 W, ~0.5 nm/s). The ALD chamber was preheated to ~225 °C; samples were dynamically heated (starting ~177 °C, rising toward 225 °C) to minimize formation of a metal–insulator interfacial layer. ALD used alternating 2 s pulses of H2O and either trimethylaluminum (TMA) at room temperature (for Al2O3) or bis(cyclopentadienyl)magnesium(II) (MgCp2) heated to 100 °C (for MgO), with 35 s N2 purges. Growth rate was ~0.11 nm per atomic layer (cycle) for both Al2O3 and MgO, enabling atomic-scale control of thickness and layer order. After M1/M2 growth, samples cooled in high vacuum and then received top Pd electrodes by sputtering (30 mTorr/45 W, ~1 nm/s). Shadow masks defined 12 devices per chip with areas 200×200, 200×300, and 200×400 μm^2.

Architectures: Multiple stacks with total M1/M2 thicknesses between 11–22 cycles (C) (~1.2–2.4 nm) were made. MgO atomic layers were inserted at specified positions in the Al2O3 stack to tune V_O concentration in M1 and/or M2. Comparative devices used an M2 formed by thermal oxidation of Al (Th-AlOx): after Al deposition, the sample was exposed to O2 at ~2 Torr for 520 s (~1040 Torr·s), producing ~1 nm Th-AlOx, followed by ALD-Al2O3 M1 growth on top.

Electrical characterization: I–V measurements (Agilent B1500) employed tungsten probe tips in a probe station. Pd was grounded; Al was biased. Initial low-voltage sweeps (±0.5 V) assessed initial resistance; HRS/LRS were read at 100 mV (where the Schottky barrier remains effective). Slight electroforming was sometimes needed (first switch at slightly higher voltage). Electrode line resistances were subtracted.

In vacuo scanning tunneling spectroscopy (STS): Half-cells (without top electrode) were characterized in UHV (~10^-10 Torr) with a PtIr tip. dI/dV spectra were collected by sweeping 0–2.3 V with a 45 mV, 5 kHz AC modulation. For each film, ~60–80 spectra were taken. Bisquare fits identified the conduction-band onset and extracted the tunnel/barrier height E_b (also denoted E_t in the text) and ALD coverage quality.

Electron microscopy: Cross-sectional HRTEM/STEM-HAADF and EDS mapping were performed (FEI Titan Themis^3, 300 kV, aberration-corrected, monochromated). Lamellae were prepared by focused ion beam (Helios ThermoFisher, Ga source). Layer-by-layer growth and elemental distributions (Al, Mg, Pd) were analyzed; line profiles across the dielectric stack assessed layer periodicity (~0.1 nm inter-peak separation expected per ALD layer).

DFT calculations: Density functional theory used VASP with PAW potentials and the HSE06 hybrid functional (mixing parameter 32%). A 120-atom supercell with periodic boundary conditions and a Γ-centered 2×2×2 k-point grid, 400 eV plane-wave cutoff, and structural relaxations to forces <10 meV/Å were used. Defect formation energies followed the Freysoldt formalism; chemical potentials were constrained to avoid MgAl2O4 formation. Charge-state corrections used sxdefectalign. Formation energies of native defects (V_O, V_Al, Al_i) and Mg-related defects (Mg_Al, Mg_O, Mg_i) were computed under Al-rich, O-rich, and μ_O = −0.65 eV (ALD-like) conditions to assess Fermi level shifts and V_O formation energetics.

• DFT predicts Mg acts as a deep acceptor in Al2O3, lowering the Fermi level (more insulating HRS) and reducing oxygen-vacancy (V_O) formation energy (promoting switching). This trend holds under Al-rich, O-rich, and μ_O = −0.65 eV conditions mimicking ALD growth.
• Atomically inserting MgO layers into pristine ALD-Al2O3 enables controlled V_O doping. STS confirms electronic structure tuning: conduction band onset rounds and barrier height E_b decreases modestly with MgO insertion, indicating controlled introduction of carriers/defects.
• Example stacks (all 17C ≈ 1.9 nm total): • Pure 17C Al2O3 (no MgO) shows large E_t ~1.79 eV, hard breakdown, and no sustainable switching (pristine dielectric). • 3 MgO layers in M1 (positions 3, 6, 9) yield E_g ~1.70 eV and occasional switching but low endurance/yield. • 1 MgO layer as M2 (position 1) yields E_g ~1.38 eV and sustainable switching, highlighting the importance of interfacial V_O near the Ohmic contact. • 1 MgO in M2 + 2 MgO in M1 (positions 1, 4, 7) yields E_g ~1.38 eV with sustainable switching and ~100% yield.
• HRTEM/EDS directly resolves ~17 layers (~2 nm total) with ~0.1 nm periodicity, confirming layer-by-layer ALD growth. Mg is localized near intended layers (≈1.5 at% measured by EDS; semi-quantitative).
• Thickness-controlled tunability (with 1C MgO in M2, M1 varied): HRS and on/off ratio increase exponentially with total thickness from 11–20C (≈1.2–2.4 nm), consistent with tunneling-dominated HRS conduction. Example: 20C device HRS ≈ 3.98 MΩ, on/off ~10^4; 14C device HRS ≈ 17.4 kΩ, on/off ~20; LRS remains relatively constant except possible upturn at 22C.
• SET/RESET voltages: SET ~1.0–1.5 V; RESET ~−2.0 to −3.5 V, within typical oxide RRAM ranges.
• Role of M2 quality: Devices with ALD-MgO M2 show higher-quality M1 (STS E_b ≈ 1.45 ± 0.08 eV) than those with Th-AlOx M2 (STS E_b ≈ 0.75 ± 0.01 eV), indicating defects in Th-AlOx propagate into M1 and degrade barriers.
• RA vs thickness fitting (tunneling model) yields total barrier height E_T: 2.64 ± 0.01 eV (ALD-MgO M2) vs 1.94 ± 0.01 eV (Th-AlOx M2). Subtracting STS-measured E_b gives Schottky barrier V_sch ≈ 1.19 ± 0.08 eV and 1.19 ± 0.01 eV, respectively, at Pd/Al2O3.
• Minimum thickness: with ALD-MgO M2, total thickness down to 11C shows on/off >10, among the smallest for ALD-based memristors reported.
• M1/M2 design and dynamic tunability: Combining MgO in both M1 and M2 improves yield up to 100% and enables dynamic tuning of on/off (up to an order of magnitude) via electric-field-driven redistribution of V_O at the M1/M2 interface. Placement of MgO too near the Schottky interface can reduce HRS/on-off (likely via V_sch reduction), while stacking MgO directly above M2 can initially lower R_0 but increase stabilized HRS after initial switching.
• Overall, Schottky and tunnel barriers act in tandem (E_T = E_b + V_sch) to produce high resistances at low read voltages; HRS conduction is dominated by tunneling.

The results demonstrate that starting from a pristine Al2O3 dielectric without an interfacial layer and then introducing MgO atomic layers provides atomic-scale control over V_O concentration and electronic structure. DFT establishes the mechanistic basis: Mg lowers the Fermi level and the V_O formation energy, simultaneously increasing HRS and enabling filament formation. Experimentally, inserting MgO at the M2 (Ohmic interface) is essential for sustainable conductive filament formation; additional MgO layers in M1 can serve as relays to ionize and transport V_O, further improving yield and enabling dynamic tuning. The exponential dependence of HRS and on/off ratio on total dielectric thickness confirms tunneling-dominated conduction in HRS, and RA fits quantify the combined effect of the tunnel barrier (E_b) and the Pd/Al2O3 Schottky barrier (V_sch ≈ 1.19 eV). Devices with ALD-MgO M2 exhibit higher E_b and E_T than those with Th-AlOx M2 due to minimized unintended defects and defect propagation into M1, enabling ultrathin operation (≈1.2–2.4 nm) with on/off tunable from ~10 to 10^4 and high yields. These findings directly address the need for atomic-scale tunability in memristors, showing that controlled MgO insertion within ALD-grown stacks can tailor resistive states, switching behavior, and device uniformity.

The study demonstrates atomic-scale controlled oxygen-vacancy doping of ultrathin pristine Al2O3 by inserting MgO atomic layers using in vacuo ALD, enabling atomically tunable memristors. DFT predicts, and experiments confirm, that Mg doping lowers the Fermi level (increasing resistivity) and reduces V_O formation energy (enhancing switching). Within 1.2–2.4 nm total thickness, HRS is tunable over three orders of magnitude and on/off from ~10 to 10^4, with further dynamic tuning (up to an order of magnitude) achieved by arranging MgO layers at the M1/M2 interface. HRS conduction is tunneling-dominated, with total barrier E_T = E_b + V_sch, where V_sch ≈ 1.19 eV at Pd/Al2O3 and E_b is higher for ALD-MgO/Al2O3 stacks without a defective interfacial layer. The approach offers a pathway to design ultrathin memristors with atomically tunable performance parameters.

• The observed decrease in HRS and on/off ratio at larger total thicknesses beyond the peak requires further systematic investigation; the authors hypothesize incomplete or difficult filament formation/annihilation above a critical thickness.
• EDS quantification of Mg content (~1.5 at%) is lower than expected and recognized as a limitation of EDS’ semi-quantitative accuracy.
• Slight electroforming was needed in some devices (first switch at higher voltage), indicating initial-state dependence.
• Data underlying the study are not publicly available due to a pending patent, limiting external validation at this time.