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90% yield production of polymer nano-memristor for in-memory computing

Engineering and Technology

90% yield production of polymer nano-memristor for in-memory computing

B. Zhang, W. Chen, et al.

Discover how a revolutionary two-dimensional conjugation strategy could transform the reliability of polymer memristors for low-power edge computing. This groundbreaking research conducted by Bin Zhang, Weilin Chen, Jianmin Zeng, and their team, achieves an unprecedented production yield of 90%, paving the way for faster responses and lower power consumption.

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~3 min • Beginner • English
Introduction
The study addresses the challenge of low yield and poor reliability in polymer memristors caused by structural inhomogeneity, which leads to random, localized resistive switching and impedes downscaling for low-power edge computing. Given the surge in data from IoT and AI applications, in-memory computing with memristive crossbars can reduce data movement and energy consumption. However, polymer devices often exhibit filamentary, site-dependent switching due to defects, grain boundaries, and non-uniform internal electric fields. The authors hypothesize that improving molecular planarity and film crystallinity via a two-dimensional conjugation design will homogenize the internal electric field and switching behavior, thereby increasing yield, reliability, and scalability while maintaining low power.
Literature Review
Prior work established memristors as candidates for dense storage and in-memory computing due to fast switching, CMOS compatibility, and low power. Polymer memristors have demonstrated mechanisms such as charge transfer, electrochemical redox, conformational change, and ion migration, but typically suffer from localized filamentary switching related to microstructural defects and anisotropy. Advances in organic electronics (OPV, OLED) show that periodic molecular ordering and enhanced π–π stacking improve charge transport. Two-dimensional conjugation in donor–acceptor polymers increases planarity, stacking, and crystallinity, improving electronic performance. Previous polymer memristor demonstrations showed feasibility of logic-in-memory and processing elements, but scaling and yield remained limited (e.g., control polymers without 2D conjugation showed stochastic switching and ≤40% yield). This work builds on these insights to engineer a 2D-conjugated redox-active polymer that produces bulk-phase, homogeneous switching with high yield and nanoscale scalability.
Methodology
Materials design and synthesis: A 2D-conjugated redox-active polymer, PBDTT-BQTPA, was synthesized via Stille coupling (Supplementary Fig. 1). The backbone contains bis(thiophene)-4,8-dihydrobenzo[1,2-b:4,5-b]dithiophene (BDTT) donor and quinoxaline acceptor (D–A) units to enhance coplanarity and π–π stacking, while triphenylamine (TPA) pendants provide redox activity for switching. Molecular weight (Mn ≈ 1.29 × 10^4, PDI 1.46) and solubility (toluene, CHCl3, DMF) were confirmed. Optical (UV-Vis, PL) and electrochemical (CV) characterization determined HOMO/LUMO (−5.54/−3.65 eV) and bandgap (~1.89 eV). Thermal stability was verified by TGA (onset 460 °C). Molecular simulations (DFT/TD-DFT, B3LYP/6-31G(d)) assessed redox effects and electrostatic potential distributions. Device fabrication: Micrometer devices had structure Au (top)/polymer/ITO (bottom). ITO/glass was cleaned (detergent, DI water, ethanol, acetone, isopropanol), polymer solutions (10 mg/mL in toluene) spin-coated (600 rpm 10 s, 2000 rpm 40 s), vacuum-dried (80 °C, overnight), thickness ~100 nm (also 80, 120 nm for thickness studies). Au top electrodes (120 nm, 0.4 × 0.4 mm^2) were thermally evaporated (10^−7 Torr) through a mask. Nanodevices were fabricated as 8 × 8 crossbar arrays on SiO2/Si using e-beam lithography and lift-off. Bottom electrodes: Ti (10 nm)/Au (20 nm). Polymer (5 mg/mL in toluene) spin-coated (4000 rpm, 40 s), vacuum-dried (80 °C, overnight). Top electrodes: Ti (15 nm)/Au (45 nm). Line width 100 nm, spacing 200 nm. Electrical characterization: Keithley 4200 with pulse unit measured I–V, switching speed, endurance, retention, and temperature stability (up to 125 °C). Bias applied to top electrode (Au), ITO grounded. Conductive AFM (C-AFM) mapped ON/OFF current (Pt-coated tip) across areas 5 µm × 5 µm down to 0.1 µm × 0.1 µm under ±1 V stressing and ±0.1 V reading. GIWAXS (PLS-II 9A, λ=1.10994 Å) probed crystallinity/orientation in pristine, thermally annealed (120 °C, 10 min), and electrically stressed (5 V, 3 min) films; out-of-plane and in-plane line cuts analyzed π–π (010) and lamellar (100) peaks. In-memory computing demos: Logic/arithmetic implemented with PBDTT-BQTPA array; 16 Boolean functions realized via sequential initialization/writing within single or anti-serial device configurations. A parallel 1-bit full adder used a 4 (BL) × 3 (WL) array; initialization and input mapping defined carry and sum outputs via WL currents. BNN simulation: A binarized LeNet-5 was constructed where C3 and FC layers (F4/F5) were mapped to memristor subarrays (64 × 64 bit-cells; each bit-cell: 1 memristor + 1 NMOS, 180 nm SMIC device models). Memristor HRS/LRS mapped to logic 0/1 and weights −1/+1; XNOR/XOR replaced MAC operations. Co-simulation leveraged PyTorch for non-array layers, PYOPUS as interface, and Cadence Spectre for array-level circuits. Offline and online training/validation used MNIST.
Key Findings
- Homogeneous bulk-phase switching: C-AFM current maps show uniform ON-state conduction across entire film; switching behavior independent of sampling location and persists after polarity reversal, contrasting filamentary switching. - Crystallinity and ordering: GIWAXS shows strong out-of-plane (010) peak at qx ≈ 1.77 Å−1 (π–π distance ≈ 3.54 Å) and in-plane (100) peak at qxy ≈ 1.17 Å−1 (lamellar spacing ≈ 5.36 Å), indicating face-on orientation and compact lateral packing; thermal/electrical annealing further enhances stacking. - Electrical performance (micrometer devices, Au/polymer/ITO): • Symmetric bipolar switching at low voltages (SET ≈ +0.30 V, RESET ≈ −0.29 V). • Switching speed ≤ 32 ns (instrument-limited). • Retention > 10^4 s; endurance > 10^8 cycles; stable up to 125 °C. • Device-to-device variation: turn-on 4.17%, turn-off 3.16%; ON resistance variation 8.29%; OFF resistance variation 6.25%. • Film-thickness dependence: thicker films show higher Roff and higher set voltage, indicating field-driven switching. • Production yield: ~90% of tested devices show repeatable bistable switching. - Nanoscale devices (100 nm line, 200 nm pitch, Pt/Ti/polymer/Au/Ti): • 200 consecutive I–V cycles show repeatability; ON/OFF ~10^3, larger than micrometer devices due to reduced leakage. • Programming voltages increase (~+1.25 V / −1.57 V); actual energy per bit ~5 × 10^−15 J. • Array yield: 58/64 devices switching (90.6%). Device-to-device variation: turn-on 5.57%, turn-off 4.57%. Example resistances: ON ≈ (6.90 ± 1.46) × 10^6 Ω (cyclic) and (5.76 ± 1.39) × 10^6 Ω (array); OFF ≈ (4.60 ± 0.97) × 10^9 Ω (cyclic) and (4.06 ± 1.18) × 10^9 Ω (array). • Scaling analysis via C-AFM indicates homogeneous switching domains with ~40 nm spacing; extrapolated ultra-low operating current suitable for sub-10 nm devices. - In-memory computing: All 16 Boolean logic operations implemented; a 1-bit full adder realized in a 4 × 3 array using five devices, with outputs read via WL currents matching truth table. - Neuromorphic acceleration (BNN): LeNet-5 BNN mapped to memristor subarrays achieves 99.23% offline accuracy on MNIST (10,000 test images) and 97.13% online after 1 epoch (60,000 images), demonstrating feasibility of two-state polymer devices for efficient in-memory inference.
Discussion
The 2D conjugation strategy enhances molecular planarity and crystallinity, yielding uniform face-on oriented, tightly packed polymer films that suppress defect-induced field concentration and eliminate stochastic filament formation. Consequently, resistive switching becomes a bulk phenomenon, independent of device location and area, which directly addresses the low-yield and variability issues of polymer memristors. The resulting devices exhibit fast, low-voltage, low-energy switching with excellent retention and endurance, and maintain performance upon scaling to ~100 nm with high production yield. This uniformity enables reliable array-level in-memory computations, including complete Boolean logic sets and arithmetic (full adder), and supports binary neural network acceleration with competitive accuracy while reducing computational and memory overhead via bit-wise operations. The findings underscore the significance of microstructural control in organic switching media to transition from filamentary to homogeneous switching, thereby improving manufacturability and system-level applicability.
Conclusion
By engineering a 2D-conjugated redox-active polymer (PBDTT-BQTPA), the study achieves homogeneous bulk-phase resistive switching with record-high ~90% yield and nanoscale scalability. Enhanced π–π stacking and crystallinity lead to low-voltage (≈±0.30 V) and fast (≤32 ns) switching, excellent reliability (retention >10^4 s, endurance >10^8 cycles), consistent device parameters (3.16%–8.29% variations), and energy down to ~10^−15 J/bit in 100 nm devices. The robust uniformity enables array-level in-memory logic and arithmetic, and effective BNN-based pattern recognition with ~99.23% accuracy. Future work could replace propeller-shaped TPA pendants with more planar redox moieties to further improve crystallinity and enable even finer scaling compatible with state-of-the-art lithography.
Limitations
- The measured switching speed (≤32 ns) is instrument-limited; true intrinsic speed remains to be established. - Triphenylamine (TPA) pendants introduce some azimuthal disorder due to their propeller shape, leaving minor crystallite orientation spread; more planar redox units may further improve uniformity and scaling. - While nanoscale arrays (8 × 8) show high yield, larger-scale array statistics and variability under diverse operating conditions (temperature/humidity, long-term cycling) require further study. - Programming voltages increase at the nanoscale, reflecting contact and field distribution changes; optimization of electrode interfaces may reduce voltages further. - Demonstrated BNN results are from simulation with measured device models; full hardware implementation with on-chip learning and peripheral overheads remains to be validated.
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