Low-cost and efficient prediction hardware for tabular data using tiny classifier circuits

A typical machine learning development cycle first maximizes model accuracy and then minimizes the footprint for deployment, which becomes difficult as models grow. We report a methodology that automatically generates tiny classifier circuits—predictor circuits for tabular-data classification—via an evolutionary algorithm that searches over logic-gate graphs to maximize training accuracy, yielding circuits with no more than ~300 logic gates. Simulated as silicon chips, these tiny classifiers use 8–18× less area and 4–8× less power than the best-performing ML baseline. Implemented as low-cost flexible chips (FlexICs), they occupy 10–75× less area, consume 13–75× less power and exhibit 6× higher yield than the most hardware-efficient ML baseline. Focusing on heterogeneous tabular data, our Boolean-function representation relates to decision trees and, combined with evolutionary search, avoids local minima typical of gradient-based methods, offering comparable prediction performance with substantially fewer hardware resources.

Konstantinos Iordanou, Timothy Atkinson, Emre Ozer, Jedrzej Kufel, Grace Aligada, John Biggs, Gavin Brown, Mikel Luján